Loading arch/arm/boot/dts/qcom/msmcobalt-cdp.dtsi +43 −0 Original line number Diff line number Diff line Loading @@ -35,3 +35,46 @@ qca,bt-vdd-pa-current-level = <0>; /* LPM/PFM */ }; }; &ufsphy1 { vdda-phy-supply = <&pmcobalt_l1>; vdda-pll-supply = <&pmcobalt_l2>; vddp-ref-clk-supply = <&pmcobalt_l26>; vdda-phy-max-microamp = <51400>; vdda-pll-max-microamp = <14600>; vddp-ref-clk-max-microamp = <100>; vddp-ref-clk-always-on; status = "ok"; }; &ufs1 { vdd-hba-supply = <&gdsc_ufs>; vdd-hba-fixed-regulator; vcc-supply = <&pmcobalt_l20>; vccq-supply = <&pmcobalt_l26>; vccq2-supply = <&pmcobalt_s4>; vcc-max-microamp = <750000>; vccq-max-microamp = <560000>; vccq2-max-microamp = <750000>; status = "ok"; }; &ufs_ice { status = "ok"; }; &sdhc_2 { vdd-supply = <&pmcobalt_l21>; qcom,vdd-voltage-level = <2950000 2960000>; qcom,vdd-current-level = <200 800000>; vdd-io-supply = <&pmcobalt_l13>; qcom,vdd-io-voltage-level = <1808000 2960000>; qcom,vdd-io-current-level = <200 22000>; qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>; qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; status = "ok"; }; arch/arm/boot/dts/qcom/msmcobalt-mtp.dtsi +43 −0 Original line number Diff line number Diff line Loading @@ -35,3 +35,46 @@ qca,bt-vdd-pa-current-level = <0>; /* LPM/PFM */ }; }; &ufsphy1 { vdda-phy-supply = <&pmcobalt_l1>; vdda-pll-supply = <&pmcobalt_l2>; vddp-ref-clk-supply = <&pmcobalt_l26>; vdda-phy-max-microamp = <51400>; vdda-pll-max-microamp = <14600>; vddp-ref-clk-max-microamp = <100>; vddp-ref-clk-always-on; status = "ok"; }; &ufs1 { vdd-hba-supply = <&gdsc_ufs>; vdd-hba-fixed-regulator; vcc-supply = <&pmcobalt_l20>; vccq-supply = <&pmcobalt_l26>; vccq2-supply = <&pmcobalt_s4>; vcc-max-microamp = <750000>; vccq-max-microamp = <560000>; vccq2-max-microamp = <750000>; status = "ok"; }; &ufs_ice { status = "ok"; }; &sdhc_2 { vdd-supply = <&pmcobalt_l21>; qcom,vdd-voltage-level = <2950000 2960000>; qcom,vdd-current-level = <200 800000>; vdd-io-supply = <&pmcobalt_l13>; qcom,vdd-io-voltage-level = <1808000 2960000>; qcom,vdd-io-current-level = <200 22000>; qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>; qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; status = "ok"; }; arch/arm/boot/dts/qcom/msmcobalt-rumi.dtsi +11 −3 Original line number Diff line number Diff line Loading @@ -21,21 +21,29 @@ reg = <0x1da7000 0xda8>, /* PHY regs */ <0x1db8000 0x100>; /* U11 user regs */ reg-names = "phy_mem", "u11_user"; vdda-phy-supply = <&pmcobalt_l28>; vdda-phy-supply = <&pmcobalt_l1>; vdda-pll-supply = <&pmcobalt_l2>; vddp-ref-clk-supply = <&pmcobalt_l26>; vdda-phy-max-microamp = <51400>; vdda-pll-max-microamp = <14600>; vddp-ref-clk-max-microamp = <100>; vddp-ref-clk-always-on; status = "ok"; }; &ufs1 { vdd-hba-supply = <&gdsc_ufs>; vdd-hba-fixed-regulator; vcc-supply = <&pmcobalt_l20>; vccq-supply = <&pmcobalt_l26>; vccq2-supply = <&pmcobalt_s4>; vcc-max-microamp = <750000>; vccq-max-microamp = <560000>; vccq2-max-microamp = <750000>; qcom,disable-lpm; rpm-level = <0>; spm-level = <0>; status = "ok"; }; Loading @@ -49,7 +57,7 @@ qcom,vdd-current-level = <200 800000>; vdd-io-supply = <&pmcobalt_l13>; qcom,vdd-io-voltage-level = <1800000 2950000>; qcom,vdd-io-voltage-level = <1808000 2960000>; qcom,vdd-io-current-level = <200 22000>; qcom,clk-rates = <400000 20000000 25000000 Loading arch/arm/boot/dts/qcom/msmcobalt-sim.dts +0 −12 Original line number Diff line number Diff line Loading @@ -33,18 +33,6 @@ qcom,xo-clk-rate = <19200000>; }; &ufsphy1 { status = "ok"; }; &ufs1 { status = "ok"; }; &ufs_ice { status = "ok"; }; &qusb_phy0 { compatible = "usb-nop-xceiv"; }; Loading arch/arm/boot/dts/qcom/msmcobalt-sim.dtsi +28 −3 Original line number Diff line number Diff line Loading @@ -18,15 +18,40 @@ pinctrl-0 = <&uart_console_active>; }; &ufsphy1 { vdda-phy-supply = <&pmcobalt_l1>; vdda-pll-supply = <&pmcobalt_l2>; vddp-ref-clk-supply = <&pmcobalt_l26>; vdda-phy-max-microamp = <51400>; vdda-pll-max-microamp = <14600>; vddp-ref-clk-max-microamp = <100>; vddp-ref-clk-always-on; status = "ok"; }; &ufs1 { vdd-hba-supply = <&gdsc_ufs>; vdd-hba-fixed-regulator; vcc-supply = <&pmcobalt_l20>; vccq-supply = <&pmcobalt_l26>; vccq2-supply = <&pmcobalt_s4>; vcc-max-microamp = <750000>; vccq-max-microamp = <560000>; vccq2-max-microamp = <750000>; status = "ok"; }; &ufs_ice { status = "ok"; }; &sdhc_2 { vdd-supply = <&pmcobalt_l21>; qcom,vdd-always-on; qcom,vdd-voltage-level = <2950000 2960000>; qcom,vdd-current-level = <200 800000>; vdd-io-supply = <&pmcobalt_l13>; qcom,vdd-io-always-on; qcom,vdd-io-voltage-level = <1808000 2950000>; qcom,vdd-io-voltage-level = <1808000 2960000>; qcom,vdd-io-current-level = <200 22000>; qcom,clk-rates = <400000 20000000 25000000 Loading Loading
arch/arm/boot/dts/qcom/msmcobalt-cdp.dtsi +43 −0 Original line number Diff line number Diff line Loading @@ -35,3 +35,46 @@ qca,bt-vdd-pa-current-level = <0>; /* LPM/PFM */ }; }; &ufsphy1 { vdda-phy-supply = <&pmcobalt_l1>; vdda-pll-supply = <&pmcobalt_l2>; vddp-ref-clk-supply = <&pmcobalt_l26>; vdda-phy-max-microamp = <51400>; vdda-pll-max-microamp = <14600>; vddp-ref-clk-max-microamp = <100>; vddp-ref-clk-always-on; status = "ok"; }; &ufs1 { vdd-hba-supply = <&gdsc_ufs>; vdd-hba-fixed-regulator; vcc-supply = <&pmcobalt_l20>; vccq-supply = <&pmcobalt_l26>; vccq2-supply = <&pmcobalt_s4>; vcc-max-microamp = <750000>; vccq-max-microamp = <560000>; vccq2-max-microamp = <750000>; status = "ok"; }; &ufs_ice { status = "ok"; }; &sdhc_2 { vdd-supply = <&pmcobalt_l21>; qcom,vdd-voltage-level = <2950000 2960000>; qcom,vdd-current-level = <200 800000>; vdd-io-supply = <&pmcobalt_l13>; qcom,vdd-io-voltage-level = <1808000 2960000>; qcom,vdd-io-current-level = <200 22000>; qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>; qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; status = "ok"; };
arch/arm/boot/dts/qcom/msmcobalt-mtp.dtsi +43 −0 Original line number Diff line number Diff line Loading @@ -35,3 +35,46 @@ qca,bt-vdd-pa-current-level = <0>; /* LPM/PFM */ }; }; &ufsphy1 { vdda-phy-supply = <&pmcobalt_l1>; vdda-pll-supply = <&pmcobalt_l2>; vddp-ref-clk-supply = <&pmcobalt_l26>; vdda-phy-max-microamp = <51400>; vdda-pll-max-microamp = <14600>; vddp-ref-clk-max-microamp = <100>; vddp-ref-clk-always-on; status = "ok"; }; &ufs1 { vdd-hba-supply = <&gdsc_ufs>; vdd-hba-fixed-regulator; vcc-supply = <&pmcobalt_l20>; vccq-supply = <&pmcobalt_l26>; vccq2-supply = <&pmcobalt_s4>; vcc-max-microamp = <750000>; vccq-max-microamp = <560000>; vccq2-max-microamp = <750000>; status = "ok"; }; &ufs_ice { status = "ok"; }; &sdhc_2 { vdd-supply = <&pmcobalt_l21>; qcom,vdd-voltage-level = <2950000 2960000>; qcom,vdd-current-level = <200 800000>; vdd-io-supply = <&pmcobalt_l13>; qcom,vdd-io-voltage-level = <1808000 2960000>; qcom,vdd-io-current-level = <200 22000>; qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>; qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; status = "ok"; };
arch/arm/boot/dts/qcom/msmcobalt-rumi.dtsi +11 −3 Original line number Diff line number Diff line Loading @@ -21,21 +21,29 @@ reg = <0x1da7000 0xda8>, /* PHY regs */ <0x1db8000 0x100>; /* U11 user regs */ reg-names = "phy_mem", "u11_user"; vdda-phy-supply = <&pmcobalt_l28>; vdda-phy-supply = <&pmcobalt_l1>; vdda-pll-supply = <&pmcobalt_l2>; vddp-ref-clk-supply = <&pmcobalt_l26>; vdda-phy-max-microamp = <51400>; vdda-pll-max-microamp = <14600>; vddp-ref-clk-max-microamp = <100>; vddp-ref-clk-always-on; status = "ok"; }; &ufs1 { vdd-hba-supply = <&gdsc_ufs>; vdd-hba-fixed-regulator; vcc-supply = <&pmcobalt_l20>; vccq-supply = <&pmcobalt_l26>; vccq2-supply = <&pmcobalt_s4>; vcc-max-microamp = <750000>; vccq-max-microamp = <560000>; vccq2-max-microamp = <750000>; qcom,disable-lpm; rpm-level = <0>; spm-level = <0>; status = "ok"; }; Loading @@ -49,7 +57,7 @@ qcom,vdd-current-level = <200 800000>; vdd-io-supply = <&pmcobalt_l13>; qcom,vdd-io-voltage-level = <1800000 2950000>; qcom,vdd-io-voltage-level = <1808000 2960000>; qcom,vdd-io-current-level = <200 22000>; qcom,clk-rates = <400000 20000000 25000000 Loading
arch/arm/boot/dts/qcom/msmcobalt-sim.dts +0 −12 Original line number Diff line number Diff line Loading @@ -33,18 +33,6 @@ qcom,xo-clk-rate = <19200000>; }; &ufsphy1 { status = "ok"; }; &ufs1 { status = "ok"; }; &ufs_ice { status = "ok"; }; &qusb_phy0 { compatible = "usb-nop-xceiv"; }; Loading
arch/arm/boot/dts/qcom/msmcobalt-sim.dtsi +28 −3 Original line number Diff line number Diff line Loading @@ -18,15 +18,40 @@ pinctrl-0 = <&uart_console_active>; }; &ufsphy1 { vdda-phy-supply = <&pmcobalt_l1>; vdda-pll-supply = <&pmcobalt_l2>; vddp-ref-clk-supply = <&pmcobalt_l26>; vdda-phy-max-microamp = <51400>; vdda-pll-max-microamp = <14600>; vddp-ref-clk-max-microamp = <100>; vddp-ref-clk-always-on; status = "ok"; }; &ufs1 { vdd-hba-supply = <&gdsc_ufs>; vdd-hba-fixed-regulator; vcc-supply = <&pmcobalt_l20>; vccq-supply = <&pmcobalt_l26>; vccq2-supply = <&pmcobalt_s4>; vcc-max-microamp = <750000>; vccq-max-microamp = <560000>; vccq2-max-microamp = <750000>; status = "ok"; }; &ufs_ice { status = "ok"; }; &sdhc_2 { vdd-supply = <&pmcobalt_l21>; qcom,vdd-always-on; qcom,vdd-voltage-level = <2950000 2960000>; qcom,vdd-current-level = <200 800000>; vdd-io-supply = <&pmcobalt_l13>; qcom,vdd-io-always-on; qcom,vdd-io-voltage-level = <1808000 2950000>; qcom,vdd-io-voltage-level = <1808000 2960000>; qcom,vdd-io-current-level = <200 22000>; qcom,clk-rates = <400000 20000000 25000000 Loading