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Commit ea251324 authored by Ben Widawsky's avatar Ben Widawsky Committed by Daniel Vetter
Browse files

drm/i915: Rename ring flush functions 



Historically we considered the render ring to have special flush
semantics and everything else to fall under a more general umbrella.
Probably by coincidence more than anything we decided to make the bsd
ring have the default *other* flush. As the new vebox ring exposes, the
bsd ring is actually the weird one. Doing this allows us to call
gen6_ring_flush for the vebox because calling blt_ring_flush would be
weird...

This patch should have no functional change.

Reviewed-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 1950de14

drivers/gpu/drm/i915/intel_ringbuffer.c

+6 −6
Original line number Diff line number Diff line
@@ -1565,7 +1565,7 @@ static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, 
		   _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));

}



static int gen6_ring_flush(struct intel_ring_buffer *ring,

static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,

			       u32 invalidate, u32 flush)

{

	uint32_t cmd;
@@ -1637,7 +1637,7 @@ gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, 


/* Blitter support (SandyBridge+) */



static int blt_ring_flush(struct intel_ring_buffer *ring,

static int gen6_ring_flush(struct intel_ring_buffer *ring,

			   u32 invalidate, u32 flush)

{

	uint32_t cmd;
@@ -1838,7 +1838,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev) 
		/* gen6 bsd needs a special wa for tail updates */

		if (IS_GEN6(dev))

			ring->write_tail = gen6_bsd_ring_write_tail;

		ring->flush = gen6_ring_flush;

		ring->flush = gen6_bsd_ring_flush;

		ring->add_request = gen6_add_request;

		ring->get_seqno = gen6_ring_get_seqno;

		ring->set_seqno = ring_set_seqno;
@@ -1887,7 +1887,7 @@ int intel_init_blt_ring_buffer(struct drm_device *dev) 


	ring->mmio_base = BLT_RING_BASE;

	ring->write_tail = ring_write_tail;

	ring->flush = blt_ring_flush;

	ring->flush = gen6_ring_flush;

	ring->add_request = gen6_add_request;

	ring->get_seqno = gen6_ring_get_seqno;

	ring->set_seqno = ring_set_seqno;