Merge tag 'for_3.15' of...

* APM X-Gene 15Gbps Multi-purpose PHY nodes

PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each

PHY (pair of lanes) has its own node.

Required properties:

- compatible		: Shall be "apm,xgene-phy".

- reg			: PHY memory resource is the SDS PHY access resource.

- #phy-cells		: Shall be 1 as it expects one argument for setting

			  the mode of the PHY. Possible values are 0 (SATA),

			  1 (SGMII), 2 (PCIe), 3 (USB), and 4 (XFI).

Optional properties:

- status		: Shall be "ok" if enabled or "disabled" if disabled.

			  Default is "ok".

- clocks		: Reference to the clock entry.

- apm,tx-eye-tuning	: Manual control to fine tune the capture of the serial

			  bit lines from the automatic calibrated position.

			  Two set of 3-tuple setting for each (up to 3)

			  supported link speed on the host. Range from 0 to

			  127 in unit of one bit period. Default is 10.

- apm,tx-eye-direction	: Eye tuning manual control direction. 0 means sample

			  data earlier than the nominal sampling point. 1 means

			  sample data later than the nominal sampling point.

			  Two set of 3-tuple setting for each (up to 3)

			  supported link speed on the host. Default is 0.

- apm,tx-boost-gain	: Frequency boost AC (LSB 3-bit) and DC (2-bit)

			  gain control. Two set of 3-tuple setting for each

			  (up to 3) supported link speed on the host. Range is

			  between 0 to 31 in unit of dB. Default is 3.

- apm,tx-amplitude	: Amplitude control. Two set of 3-tuple setting for

			  each (up to 3) supported link speed on the host.

			  Range is between 0 to 199500 in unit of uV.

			  Default is 199500 uV.

- apm,tx-pre-cursor1	: 1st pre-cursor emphasis taps control. Two set of

			  3-tuple setting for each (up to 3) supported link

			  speed on the host. Range is 0 to 273000 in unit of

			  uV. Default is 0.

- apm,tx-pre-cursor2	: 2st pre-cursor emphasis taps control. Two set of

			  3-tuple setting for each (up to 3) supported link

			  speed on the host. Range is 0 to 127400 in unit uV.

			  Default is 0x0.

- apm,tx-post-cursor	: Post-cursor emphasis taps control. Two set of

			  3-tuple setting for Gen1, Gen2, and Gen3. Range is

			  between 0 to 0x1f in unit of 18.2mV. Default is 0xf.

- apm,tx-speed		: Tx operating speed. One set of 3-tuple for each

			  supported link speed on the host.

			   0 = 1-2Gbps

			   1 = 2-4Gbps (1st tuple default)

			   2 = 4-8Gbps

			   3 = 8-15Gbps (2nd tuple default)

			   4 = 2.5-4Gbps

			   5 = 4-5Gbps

			   6 = 5-6Gbps

			   7 = 6-16Gbps (3rd tuple default)

NOTE: PHY override parameters are board specific setting.

Example:

		phy1: phy@1f21a000 {

			compatible = "apm,xgene-phy";

			reg = <0x0 0x1f21a000 0x0 0x100>;

			#phy-cells = <1>;

			status = "disabled";

		};

		phy2: phy@1f22a000 {

			compatible = "apm,xgene-phy";

			reg = <0x0 0x1f22a000 0x0 0x100>;

			#phy-cells = <1>;

			status = "ok";

		};

		phy3: phy@1f23a000 {

			compatible = "apm,xgene-phy";

			reg = <0x0 0x1f23a000 0x0 0x100>;

			#phy-cells = <1>;

			status = "ok";

		};

- compatible : should be "samsung,exynos5250-dp-video-phy";

- reg : offset and length of the Display Port PHY register set;

- #phy-cells : from the generic PHY bindings, must be 0;

Samsung S5P/EXYNOS SoC series USB PHY

-------------------------------------------------

Required properties:

- compatible : should be one of the listed compatibles:

	- "samsung,exynos4210-usb2-phy"

	- "samsung,exynos4x12-usb2-phy"

	- "samsung,exynos5250-usb2-phy"

- reg : a list of registers used by phy driver

	- first and obligatory is the location of phy modules registers

- samsung,sysreg-phandle - handle to syscon used to control the system registers

- samsung,pmureg-phandle - handle to syscon used to control PMU registers

- #phy-cells : from the generic phy bindings, must be 1;

- clocks and clock-names:

	- the "phy" clock is required by the phy module, used as a gate

	- the "ref" clock is used to get the rate of the clock provided to the

	  PHY module

The first phandle argument in the PHY specifier identifies the PHY, its

meaning is compatible dependent. For the currently supported SoCs (Exynos 4210

and Exynos 4212) it is as follows:

  0 - USB device ("device"),

  1 - USB host ("host"),

  2 - HSIC0 ("hsic0"),

  3 - HSIC1 ("hsic1"),

Exynos 4210 and Exynos 4212 use mode switching and require that mode switch

register is supplied.

Example:

For Exynos 4412 (compatible with Exynos 4212):

usbphy: phy@125b0000 {

	compatible = "samsung,exynos4x12-usb2-phy";

	reg = <0x125b0000 0x100>;

	clocks = <&clock 305>, <&clock 2>;

	clock-names = "phy", "ref";

	status = "okay";

	#phy-cells = <1>;

	samsung,sysreg-phandle = <&sys_reg>;

	samsung,pmureg-phandle = <&pmu_reg>;

};

Then the PHY can be used in other nodes such as:

phy-consumer@12340000 {

	phys = <&usbphy 2>;

	phy-names = "phy";

};

Refer to DT bindings documentation of particular PHY consumer devices for more

information about required PHYs and the way of specification.

Allwinner sun4i USB PHY

-----------------------

Required properties:

- compatible : should be one of "allwinner,sun4i-a10-usb-phy",

  "allwinner,sun5i-a13-usb-phy" or "allwinner,sun7i-a20-usb-phy"

- reg : a list of offset + length pairs

- reg-names : "phy_ctrl", "pmu1" and for sun4i or sun7i "pmu2"

- #phy-cells : from the generic phy bindings, must be 1

- clocks : phandle + clock specifier for the phy clock

- clock-names : "usb_phy"

- resets : a list of phandle + reset specifier pairs

- reset-names : "usb0_reset", "usb1_reset" and for sun4i or sun7i "usb2_reset"

Example:

	usbphy: phy@0x01c13400 {

		#phy-cells = <1>;

		compatible = "allwinner,sun4i-a10-usb-phy";

		/* phy base regs, phy1 pmu reg, phy2 pmu reg */

		reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;

		reg-names = "phy_ctrl", "pmu1", "pmu2";

		clocks = <&usb_clk 8>;

		clock-names = "usb_phy";

		resets = <&usb_clk 1>, <&usb_clk 2>;

		reset-names = "usb1_reset", "usb2_reset";

	};

.------------------------------------------------------------------------------+

|			Samsung USB 2.0 PHY adaptation layer		       |

+-----------------------------------------------------------------------------+'

| 1. Description

+----------------

The architecture of the USB 2.0 PHY module in Samsung SoCs is similar

among many SoCs. In spite of the similarities it proved difficult to

create a one driver that would fit all these PHY controllers. Often

the differences were minor and were found in particular bits of the

registers of the PHY. In some rare cases the order of register writes or

the PHY powering up process had to be altered. This adaptation layer is

a compromise between having separate drivers and having a single driver

with added support for many special cases.

| 2. Files description

+----------------------

- phy-samsung-usb2.c

   This is the main file of the adaptation layer. This file contains

   the probe function and provides two callbacks to the Generic PHY

   Framework. This two callbacks are used to power on and power off the

   phy. They carry out the common work that has to be done on all version

   of the PHY module. Depending on which SoC was chosen they execute SoC

   specific callbacks. The specific SoC version is selected by choosing

   the appropriate compatible string. In addition, this file contains

   struct of_device_id definitions for particular SoCs.

- phy-samsung-usb2.h

   This is the include file. It declares the structures used by this

   driver. In addition it should contain extern declarations for

   structures that describe particular SoCs.

| 3. Supporting SoCs

+--------------------

To support a new SoC a new file should be added to the drivers/phy

directory. Each SoC's configuration is stored in an instance of the

struct samsung_usb2_phy_config.

struct samsung_usb2_phy_config {

	const struct samsung_usb2_common_phy *phys;

	int (*rate_to_clk)(unsigned long, u32 *);

	unsigned int num_phys;

	bool has_mode_switch;

};

The num_phys is the number of phys handled by the driver. *phys is an

array that contains the configuration for each phy. The has_mode_switch

property is a boolean flag that determines whether the SoC has USB host

and device on a single pair of pins. If so, a special register has to

be modified to change the internal routing of these pins between a USB

device or host module.

For example the configuration for Exynos 4210 is following:

const struct samsung_usb2_phy_config exynos4210_usb2_phy_config = {

	.has_mode_switch        = 0,

	.num_phys		= EXYNOS4210_NUM_PHYS,

	.phys			= exynos4210_phys,

	.rate_to_clk		= exynos4210_rate_to_clk,

}

- int (*rate_to_clk)(unsigned long, u32 *)

	The rate_to_clk callback is to convert the rate of the clock

	used as the reference clock for the PHY module to the value

	that should be written in the hardware register.

The exynos4210_phys configuration array is as follows:

static const struct samsung_usb2_common_phy exynos4210_phys[] = {

	{

		.label		= "device",

		.id		= EXYNOS4210_DEVICE,

		.power_on	= exynos4210_power_on,

		.power_off	= exynos4210_power_off,

	},

	{

		.label		= "host",

		.id		= EXYNOS4210_HOST,

		.power_on	= exynos4210_power_on,

		.power_off	= exynos4210_power_off,

	},

	{

		.label		= "hsic0",

		.id		= EXYNOS4210_HSIC0,

		.power_on	= exynos4210_power_on,

		.power_off	= exynos4210_power_off,

	},

	{

		.label		= "hsic1",

		.id		= EXYNOS4210_HSIC1,

		.power_on	= exynos4210_power_on,

		.power_off	= exynos4210_power_off,

	},

	{},

};

- int (*power_on)(struct samsung_usb2_phy_instance *);

- int (*power_off)(struct samsung_usb2_phy_instance *);

	These two callbacks are used to power on and power off the phy

	by modifying appropriate registers.

Final change to the driver is adding appropriate compatible value to the

phy-samsung-usb2.c file. In case of Exynos 4210 the following lines were

added to the struct of_device_id samsung_usb2_phy_of_match[] array:

#ifdef CONFIG_PHY_EXYNOS4210_USB2

	{

		.compatible = "samsung,exynos4210-usb2-phy",

		.data = &exynos4210_usb2_phy_config,

	},

#endif

To add further flexibility to the driver the Kconfig file enables to

include support for selected SoCs in the compiled driver. The Kconfig

entry for Exynos 4210 is following:

config PHY_EXYNOS4210_USB2

	bool "Support for Exynos 4210"

	depends on PHY_SAMSUNG_USB2

	depends on CPU_EXYNOS4210

	help

	  Enable USB PHY support for Exynos 4210. This option requires that

	  Samsung USB 2.0 PHY driver is enabled and means that support for this

	  particular SoC is compiled in the driver. In case of Exynos 4210 four

	  phys are available - device, host, HSCI0 and HSCI1.

The newly created file that supports the new SoC has to be also added to the

Makefile. In case of Exynos 4210 the added line is following:

obj-$(CONFIG_PHY_EXYNOS4210_USB2)       += phy-exynos4210-usb2.o

After completing these steps the support for the new SoC should be ready.

	  framework should select this config.

config PHY_EXYNOS_MIPI_VIDEO

	depends on HAS_IOMEM

	tristate "S5P/EXYNOS SoC series MIPI CSI-2/DSI PHY driver"

	depends on HAS_IOMEM

	depends on ARCH_S5PV210 || ARCH_EXYNOS || COMPILE_TEST

	select GENERIC_PHY

	default y if ARCH_S5PV210 || ARCH_EXYNOS

	help

	  Support for MIPI CSI-2 and MIPI DSI DPHY found on Samsung S5P

	  and EXYNOS SoCs.

config PHY_MVEBU_SATA

	def_bool y

	depends on ARCH_KIRKWOOD || ARCH_DOVE

	depends on ARCH_KIRKWOOD || ARCH_DOVE || MACH_DOVE

	depends on OF

	select GENERIC_PHY

config OMAP_CONTROL_PHY

	tristate "OMAP CONTROL PHY Driver"

	help

	  Enable this to add support for the PHY part present in the control

	  module. This driver has API to power on the USB2 PHY and to write to

	  the mailbox. The mailbox is present only in omap4 and the register to

	  power on the USB2 PHY is present in OMAP4 and OMAP5. OMAP5 has an

	  additional register to power on USB3 PHY/SATA PHY/PCIE PHY

	  (PIPE3 PHY).

config OMAP_USB2

	tristate "OMAP USB2 PHY Driver"

	depends on ARCH_OMAP2PLUS

	depends on USB_PHY

	select GENERIC_PHY

	select OMAP_CONTROL_USB

	select OMAP_CONTROL_PHY

	depends on OMAP_OCP2SCP

	help

	  Enable this to support the transceiver that is part of SOC. This

	  driver takes care of all the PHY functionality apart from comparator.

	  The USB OTG controller communicates with the comparator using this

	  driver.

config TI_PIPE3

	tristate "TI PIPE3 PHY Driver"

	depends on ARCH_OMAP2PLUS || COMPILE_TEST

	select GENERIC_PHY

	select OMAP_CONTROL_PHY

	depends on OMAP_OCP2SCP

	help

	  Enable this to support the PIPE3 PHY that is part of TI SOCs. This

	  driver takes care of all the PHY functionality apart from comparator.

	  This driver interacts with the "OMAP Control PHY Driver" to power

	  on/off the PHY.

config TWL4030_USB

	tristate "TWL4030 USB Transceiver Driver"

	depends on TWL4030_CORE && REGULATOR_TWL4030 && USB_MUSB_OMAP2PLUS

config PHY_EXYNOS_DP_VIDEO

	tristate "EXYNOS SoC series Display Port PHY driver"

	depends on OF

	depends on ARCH_EXYNOS || COMPILE_TEST

	default ARCH_EXYNOS

	select GENERIC_PHY

	help

	  Support for Display Port PHY found on Samsung EXYNOS SoCs.

	help

	  Enable this to support the Broadcom Kona USB 2.0 PHY.

config PHY_EXYNOS5250_SATA

	tristate "Exynos5250 Sata SerDes/PHY driver"

	depends on SOC_EXYNOS5250

	depends on HAS_IOMEM

	depends on OF

	select GENERIC_PHY

	select I2C

	select I2C_S3C2410

	select MFD_SYSCON

	help

	  Enable this to support SATA SerDes/Phy found on Samsung's

	  Exynos5250 based SoCs.This SerDes/Phy supports SATA 1.5 Gb/s,

	  SATA 3.0 Gb/s, SATA 6.0 Gb/s speeds. It supports one SATA host

	  port to accept one SATA device.

config PHY_SUN4I_USB

	tristate "Allwinner sunxi SoC USB PHY driver"

	depends on ARCH_SUNXI && HAS_IOMEM && OF

	select GENERIC_PHY

	help

	  Enable this to support the transceiver that is part of Allwinner

	  sunxi SoCs.

	  This driver controls the entire USB PHY block, both the USB OTG

	  parts, as well as the 2 regular USB 2 host PHYs.

config PHY_SAMSUNG_USB2

	tristate "Samsung USB 2.0 PHY driver"

	select GENERIC_PHY

	select MFD_SYSCON

	help

	  Enable this to support the Samsung USB 2.0 PHY driver for Samsung

	  SoCs. This driver provides the interface for USB 2.0 PHY. Support for

	  particular SoCs has to be enabled in addition to this driver. Number

	  and type of supported phys depends on the SoC.

config PHY_EXYNOS4210_USB2

	bool "Support for Exynos 4210"

	depends on PHY_SAMSUNG_USB2

	depends on CPU_EXYNOS4210

	help

	  Enable USB PHY support for Exynos 4210. This option requires that

	  Samsung USB 2.0 PHY driver is enabled and means that support for this

	  particular SoC is compiled in the driver. In case of Exynos 4210 four

	  phys are available - device, host, HSIC0 and HSIC1.

config PHY_EXYNOS4X12_USB2

	bool "Support for Exynos 4x12"

	depends on PHY_SAMSUNG_USB2

	depends on (SOC_EXYNOS4212 || SOC_EXYNOS4412)

	help

	  Enable USB PHY support for Exynos 4x12. This option requires that

	  Samsung USB 2.0 PHY driver is enabled and means that support for this

	  particular SoC is compiled in the driver. In case of Exynos 4x12 four

	  phys are available - device, host, HSIC0 and HSIC1.

config PHY_EXYNOS5250_USB2

	bool "Support for Exynos 5250"

	depends on PHY_SAMSUNG_USB2

	depends on SOC_EXYNOS5250

	help

	  Enable USB PHY support for Exynos 5250. This option requires that

	  Samsung USB 2.0 PHY driver is enabled and means that support for this

	  particular SoC is compiled in the driver. In case of Exynos 5250 four

	  phys are available - device, host, HSIC0 and HSIC.

config PHY_XGENE

	tristate "APM X-Gene 15Gbps PHY support"

	depends on HAS_IOMEM && OF && (ARM64 || COMPILE_TEST)

	select GENERIC_PHY

	help

	  This option enables support for APM X-Gene SoC multi-purpose PHY.

endmenu