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Commit ea1009fe authored by Abhishek Kondaveeti's avatar Abhishek Kondaveeti
Browse files

ARM: dts: msm: Add support for 8952 ISP 



Add support for 8952 ISP and ISPIF hardware.

Change-Id: I2d69a1caa56426159023ff7d177f3956ef95f7dc
Signed-off-by: default avatarAbhishek Kondaveeti <akondave@codeaurora.org>
parent 95314eae

arch/arm/boot/dts/qcom/msm8952-camera.dtsi

+116 −105
Original line number Original line Diff line number Diff line
@@ -138,7 +138,6 @@ 
	};

	};





	qcom,ispif@1b0a000 {

	qcom,ispif@1b0a000 {

		status = "disabled";

		cell-index = <0>;

		cell-index = <0>;

		compatible = "qcom,ispif-v3.0", "qcom,ispif";

		compatible = "qcom,ispif-v3.0", "qcom,ispif";

		reg = <0x1b0a000 0x500>,

		reg = <0x1b0a000 0x500>,
@@ -147,6 +146,8 @@ 
		interrupts = <0 55 0>;

		interrupts = <0 55 0>;

		interrupt-names = "ispif";

		interrupt-names = "ispif";

		qcom,num-isps = <0x2>;

		qcom,num-isps = <0x2>;

		vfe0_vdd_supply = <&gdsc_vfe>;

		vfe1_vdd_supply = <&gdsc_vfe1>;

		clocks = <&clock_gcc clk_gcc_camss_ispif_ahb_clk>,

		clocks = <&clock_gcc clk_gcc_camss_ispif_ahb_clk>,

			<&clock_gcc clk_csi0_clk_src>,

			<&clock_gcc clk_csi0_clk_src>,

			<&clock_gcc clk_gcc_camss_csi0_clk>,

			<&clock_gcc clk_gcc_camss_csi0_clk>,
@@ -175,16 +176,25 @@ 
			"csi2_rdi_clk", "csi2_pix_clk",

			"csi2_rdi_clk", "csi2_pix_clk",

			"vfe0_clk_src", "camss_vfe_vfe0_clk", "camss_csi_vfe0_clk",

			"vfe0_clk_src", "camss_vfe_vfe0_clk", "camss_csi_vfe0_clk",

			"vfe1_clk_src", "camss_vfe_vfe1_clk", "camss_csi_vfe1_clk";

			"vfe1_clk_src", "camss_vfe_vfe1_clk", "camss_csi_vfe1_clk";

		qcom,clock-rates = "61540000",

		qcom,clock-rates = <61540000

			"200000000", "0", "0", "0",

			200000000 0 0 0

			"200000000", "0", "0", "0",

			200000000 0 0 0

			"200000000", "0", "0", "0",

			200000000 0 0 0

			"0", "0", "0",

			0 0 0

			"0", "0", "0";

			0 0 0>;

		qcom,clock-control = "SET_RATE",

			"SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",

			"SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",

			"SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",

			"INIT_RATE", "NO_SET_RATE", "NO_SET_RATE",

			"INIT_RATE", "NO_SET_RATE", "NO_SET_RATE";

	};

	};





	vfe0: qcom,vfe@1b10000 {

	qcom,vfe {

		status = "disabled";

		compatible = "qcom,vfe";

		ranges;



		vfe0: qcom,vfe0@1b10000 {

			cell-index = <0>;

			cell-index = <0>;

			compatible = "qcom,vfe40";

			compatible = "qcom,vfe40";

			reg = <0x1b10000 0x1000>,

			reg = <0x1b10000 0x1000>,
@@ -202,8 +212,9 @@ 
				<&clock_gcc clk_gcc_camss_vfe_axi_clk>,

				<&clock_gcc clk_gcc_camss_vfe_axi_clk>,

				<&clock_gcc clk_gcc_camss_ispif_ahb_clk>;

				<&clock_gcc clk_gcc_camss_ispif_ahb_clk>;

			clock-names = "camss_top_ahb_clk", "camss_ahb_clk",

			clock-names = "camss_top_ahb_clk", "camss_ahb_clk",

			"vfe_clk_src", "camss_vfe_vfe_clk", "camss_csi_vfe_clk",

				"vfe_clk_src", "camss_vfe_vfe_clk",

			"iface_clk", "bus_clk", "iface_ahb_clk";

				"camss_csi_vfe_clk", "iface_clk",

				"bus_clk", "iface_ahb_clk";

			qcom,clock-rates = <0 0 266670000 0 0 0 0 0>;

			qcom,clock-rates = <0 0 266670000 0 0 0 0 0>;

			qos-entries = <8>;

			qos-entries = <8>;

			qos-regs = <0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8

			qos-regs = <0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8
@@ -233,8 +244,7 @@ 
			max-clk-turbo = <360000000>;

			max-clk-turbo = <360000000>;

		};

		};





	vfe1: qcom,vfe@1b14000 {

		vfe1: qcom,vfe1@1b14000 {

		status = "disabled";

			cell-index = <1>;

			cell-index = <1>;

			compatible = "qcom,vfe40";

			compatible = "qcom,vfe40";

			reg = <0x1b14000 0x1000>,

			reg = <0x1b14000 0x1000>,
@@ -252,8 +262,9 @@ 
				<&clock_gcc clk_gcc_camss_vfe1_axi_clk>,

				<&clock_gcc clk_gcc_camss_vfe1_axi_clk>,

				<&clock_gcc clk_gcc_camss_ispif_ahb_clk>;

				<&clock_gcc clk_gcc_camss_ispif_ahb_clk>;

			clock-names = "camss_top_ahb_clk" , "camss_ahb_clk",

			clock-names = "camss_top_ahb_clk" , "camss_ahb_clk",

			"vfe_clk_src", "camss_vfe_vfe_clk", "camss_csi_vfe_clk",

				"vfe_clk_src", "camss_vfe_vfe_clk",

			"iface_clk", "bus_clk", "iface_ahb_clk";

				"camss_csi_vfe_clk", "iface_clk",

				"bus_clk", "iface_ahb_clk";

			qcom,clock-rates = <0 0 266670000 0 0 0 0 0>;

			qcom,clock-rates = <0 0 266670000 0 0 0 0 0>;

			qos-entries = <8>;

			qos-entries = <8>;

			qos-regs = <0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8

			qos-regs = <0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8
@@ -282,7 +293,7 @@ 
			max-clk-nominal = <308570000>;

			max-clk-nominal = <308570000>;

			max-clk-turbo = <360000000>;

			max-clk-turbo = <360000000>;

		};

		};



	};

	qcom,cam_smmu {

	qcom,cam_smmu {

		status = "disabled";

		status = "disabled";

		compatible = "qcom,msm-cam-smmu";

		compatible = "qcom,msm-cam-smmu";