Loading Documentation/devicetree/bindings/arm/msm/qcom,osm.txt 0 → 100644 +359 −0 Original line number Diff line number Diff line Qualcomm Technologies, Inc. OSM Bindings Operating State Manager (OSM) is a hardware engine used by some Qualcomm Technologies, Inc. (QTI) SoCs to manage frequency and voltage scaling in hardware. OSM is capable of controlling frequency and voltage requests for multiple clusters via the existence of multiple OSM domains. Properties: - compatible Usage: required Value type: <string> Definition: must be "qcom,cpu-clock-osm". - reg Usage: required Value type: <prop-encoded-array> Definition: Addresses and sizes for the memory of the OSM controller and cluster PLL management. - reg-names Usage: required Value type: <stringlist> Definition: Address names. Must be "osm", "pwrcl_pll", and "perfcl_pll." Must be specified in the same order as the corresponding addresses are specified in the reg property. - vdd-pwrcl-supply Usage: required Value type: <phandle> Definition: phandle of the underlying regulator device that manages the voltage supply of the Power cluster. - vdd-perfcl-supply Usage: required Value type: <phandle> Definition: phandle of the underlying regulator device that manages the voltage supply of the Performance cluster. - interrupts Usage: required Value type: <prop-encoded-array> Definition: OSM interrupt specifier. - interrupt-names Usage: required Value type: <stringlist> Definition: Interrupt names. this list must match up 1-to-1 with the interrupts specified in the 'interrupts' property. "pwrcl-irq" and "perfcl-irq" must be specified. - qcom,pwrcl-speedbinX-v0 Usage: required Value type: <prop-encoded-array> Definition: Array which defines the frequency in Hertz, frequency, and PLL override data used by the OSM hardware for each supported DCVS setpoint of the Power cluster. - qcom,perfcl-speedbinX-v0 Usage: required Value type: <prop-encoded-array> Definition: Array which defines the frequency in Hertz, frequency, and PLL override data used by the OSM hardware for each supported DCVS setpoint of the Performance cluster. - qcom,osm-no-tz Usage: optional Value type: <empty> Definition: Boolean flag which indicates that there is no programming of the OSM hardware performed by the secure world. - qcom,osm-pll-setup Usage: optional Value type: <empty> Definition: Boolean flag which indicates that the PLL setup sequence must be executed for each clock domain managed by the OSM controller. - qcom,up-timer Usage: optional Value type: <prop-encoded-array> Definition: Array which defines the DCVS up timer value in microseconds for each of the two clusters managed by the OSM controller. - qcom,down-timer Usage: optional Value type: <prop-encoded-array> Definition: Array which defines the DCVS down timer value in microseconds for each of the two clusters managed by the OSM controller. - qcom,pc-override-index Usage: optional Value type: <prop-encoded-array> Definition: Array which defines the OSM performance index to be used when each cluster enters certain low power modes. - qcom,set-ret-inactive Usage: optional Value type: <empty> Definition: Boolean flag which indicates if domains in retention must be treated as inactive. - qcom,enable-llm-freq-vote Usage: optional Value type: <empty> Definition: Boolean flag which indicates if Limits hardware frequency votes must be honored by OSM. - qcom,llm-freq-up-timer Usage: optional Value type: <prop-encoded-array> Definition: Array which devines the LLM frequency up timer value in microseconds for each of the two clusters managed by the OSM controller. - qcom,llm-freq-down-timer Usage: optional Value type: <prop-encoded-array> Definition: Array which devines the LLM frequency down timer value in microseconds for each of the two clusters managed by the OSM controller. - qcom,enable-llm-volt-vote Usage: optional Value type: <empty> Definition: Boolean flag which indicates if Limits hardware voltage votes must be honored by OSM. - qcom,llm-volt-up-timer Usage: optional Value type: <prop-encoded-array> Definition: Array which devines the LLM voltage up timer value in microseconds for each of the two clusters managed by the OSM controller. - qcom,llm-volt-down-timer Usage: optional Value type: <prop-encoded-array> Definition: Array which devines the LLM voltage down timer value in microseconds for each of the two clusters managed by the OSM controller. - qcom,cc-reads Usage: optional Value type: <integer> Definition: Defines the number of times the cycle counters must be read to determine the performance level of each clock domain. - qcom,l-val-base Usage: required Value type: <prop-encoded-array> Definition: Array which defines the register addresses of the L_VAL control register for each of the two clusters managed by the OSM controller. - qcom,apcs-itm-present Usage: required Value type: <prop-encoded-array> Definition: Array which defines the register addresses of the ITM control register for each of the two clusters managed by the OSM controller. - qcom,apcs-pll-user-ctl Usage: required Value type: <prop-encoded-array> Definition: Array which defines the register addresses of the PLL user control register for each of the two clusters managed by the OSM controller. - qcom,apcs-cfg-rcgr Usage: required Value type: <prop-encoded-array> Definition: Array which defines the register addresses of the RCGR configuration register for each of the two clusters managed by the OSM controller. - qcom,apcs-cmd-rcgr Usage: required Value type: <prop-encoded-array> Definition: Array which defines the register addresses of the RCGR command register for each of the two clusters managed by the OSM controller. - qcom,apm-mode-ctl Usage: required Value type: <prop-encoded-array> Definition: Array which defines the register addresses of the APM control register for each of the two clusters managed by the OSM controller. - qcom,apm-ctrl-status Usage: required Value type: <prop-encoded-array> Definition: Array which defines the register addresses of the APM controller status register for each of the two clusters managed by the OSM controller. - qcom,red-fsm-en Usage: optional Value type: <empty> Definition: Boolean flag which indicates if the reduction FSM should be enabled. - qcom,boost-fsm-en Usage: optional Value type: <empty> Definition: Boolean flag which indicates if the boost FSM should be enabled. - qcom,safe-fsm-en Usage: optional Value type: <empty> Definition: Boolean flag which indicates if the safe FSM should be enabled. - qcom,ps-fsm-en Usage: optional Value type: <empty> Definition: Boolean flag which indicates if the PS FSM should be enabled. - qcom,droop-fsm-en Usage: optional Value type: <empty> Definition: Boolean flag which indicates if the droop FSM should be enabled. - qcom,wfx-fsm-en Usage: optional Value type: <empty> Definition: Boolean flag which indicates if the WFX FSM should be enabled. - qcom,pc-fsm-en Usage: optional Value type: <empty> Definition: Boolean flag which indicates if the PC/RET FSM should be enabled. - clock-names Usage: required Value type: <string> Definition: Must be "aux_clk". - clocks Usage: required Value type: <phandle> Definition: Phandle to the aux clock device. Example: clock_cpu: qcom,cpu-clock-cobalt@179c0000 { compatible = "qcom,cpu-clock-osm"; reg = <0x179C0000 0x4000>, <0x17916000 0x1000>, <0x17816000 0x1000>; reg-names = "osm", "pwrcl_pll", "perfcl_pll"; vdd-pwrcl-supply = <&apc0_pwrcl_vreg>; vdd-perfcl-supply = <&apc1_perfcl_vreg>; interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>; interrupt-names = "pwrcl-irq", "perfcl-irq"; qcom,pwrcl-speedbin0-v0 = < 300000000 0x4000f 0x31e001e >, < 345600000 0x5040012 0x4200020 >, < 422400000 0x5040016 0x4200020 >, < 499200000 0x504001a 0x5200020 >, < 576000000 0x504001e 0x6200020 >, < 633600000 0x4040021 0x7200020 >, < 710400000 0x4040025 0x7200020 >, < 806400000 0x404002a 0x8220022 >, < 883200000 0x404002e 0x9250025 >, < 960000000 0x4040032 0xa280028 >, < 1036800000 0x4040036 0xb2b002b >, < 1113600000 0x404003a 0xc2e002e >, < 1190400000 0x404003e 0xc320032 >, < 1248000000 0x4040041 0xd340034 >, < 1324800000 0x4040045 0xe370037 >, < 1401600000 0x4040049 0xf3a003a >, < 1478400000 0x404004d 0x103e003e >, < 1497600000 0x404004e 0x103e003e >, < 1574400000 0x4040052 0x10420042 >, < 1651200000 0x4040056 0x11450045 >, < 1728000000 0x404005a 0x12480048 >, < 1804800000 0x404005e 0x134b004b >, < 1881600000 0x4040062 0x144e004e >; qcom,perfcl-speedbin0-v0 = < 300000000 0x4000f 0x3200020 >, < 345600000 0x5040012 0x4200020 >, < 422400000 0x5040016 0x4200020 >, < 480000000 0x5040019 0x5200020 >, < 556800000 0x504001d 0x6200020 >, < 633600000 0x4040021 0x7200020 >, < 710400000 0x4040025 0x7200020 >, < 787200000 0x4040029 0x8210021 >, < 844800000 0x404002c 0x9240024 >, < 902400000 0x404002f 0x9260026 >, < 979200000 0x4040033 0xa290029 >, < 1056000000 0x4040037 0xb2c002c >, < 1094400000 0x4040039 0xb2e002e >, < 1171200000 0x404003d 0xc300030 >, < 1248000000 0x4040041 0xd340034 >, < 1324800000 0x4040045 0xe370037 >, < 1401600000 0x4040049 0xf3b003b >, < 1478400000 0x404004d 0xf3e003e >, < 1536000000 0x4040050 0x10400040 >, < 1632000000 0x4040055 0x11440044 >, < 1708800000 0x4040059 0x12480048 >, < 1785600000 0x404005d 0x134a004a >, < 1862400000 0x4040061 0x134e004e >, < 1939200000 0x4040065 0x14510051 >, < 2016000000 0x4040069 0x15540054 >, < 2092800000 0x404006d 0x16570057 >; qcom,osm-no-tz; qcom,osm-pll-setup; qcom,up-timer = <1 1>; qcom,down-timer = <1 1>; qcom,pc-override-index = <0 0>; qcom,set-ret-inactive; qcom,enable-llm-freq-vote; qcom,llm-freq-up-timer = <1 1>; qcom,llm-freq-down-timer = <1 1>; qcom,enable-llm-volt-vote; qcom,llm-volt-up-timer = <1 1>; qcom,llm-volt-down-timer = <1 1>; qcom,cc-reads = <10>; qcom,l-val-base = <0x17916004 0x17816004>; qcom,apcs-itm-present = <0x179d143c 0x179d143c>; qcom,apcs-pll-user-ctl = <0x1791600c 0x1781600c>; qcom,apcs-cfg-rcgr = <0x17911054 0x17811054>; qcom,apcs-cmd-rcgr = <0x17911050 0x17811050>; qcom,apm-mode-ctl = <0x179d0004 0x179d0010>; qcom,apm-ctrl-status = <0x179d000c 0x179d0018>; clock-names = "aux_clk"; clocks = <&clock_gcc clk_gpll0_ao>; #clock-cells = <1>; }; } Documentation/devicetree/bindings/regulator/cprh-kbss-regulator.txt 0 → 100644 +411 −0 File added.Preview size limit exceeded, changes collapsed. Show changes arch/arm/boot/dts/qcom/msmcobalt-regulator.dtsi +149 −0 Original line number Diff line number Diff line Loading @@ -528,3 +528,152 @@ }; }; &soc { /* CPR controller regulators */ apc0_cpr: cprh-ctrl@179c8000 { compatible = "qcom,cprh-msmcobalt-kbss-regulator"; reg = <0x179c8000 0x4000>, <0x00784000 0x1000>; reg-names = "cpr_ctrl", "fuse_base"; clocks = <&clock_gcc clk_gcc_hmss_rbcpr_clk>; clock-names = "core_clk"; qcom,cpr-ctrl-name = "apc0"; qcom,cpr-controller-id = <0>; qcom,cpr-sensor-time = <1000>; qcom,cpr-loop-time = <5000000>; qcom,cpr-idle-cycles = <15>; qcom,cpr-up-down-delay-time = <3000>; qcom,cpr-step-quot-init-min = <11>; qcom,cpr-step-quot-init-max = <13>; qcom,cpr-count-mode = <2>; /* Staggered */ qcom,cpr-down-error-step-limit = <1>; qcom,cpr-up-error-step-limit = <1>; qcom,cpr-corner-switch-delay-time = <1600>; qcom,cpr-voltage-settling-time = <1600>; qcom,apm-threshold-voltage = <800000>; qcom,apm-hysteresis-voltage = <4000>; qcom,voltage-step = <4000>; qcom,voltage-base = <352000>; qcom,cpr-saw-use-unit-mV; thread@0 { qcom,cpr-thread-id = <0>; qcom,cpr-consecutive-up = <0>; qcom,cpr-consecutive-down = <2>; qcom,cpr-up-threshold = <0>; qcom,cpr-down-threshold = <2>; apc0_pwrcl_vreg: regulator-pwrcl { regulator-name = "apc0_pwrcl_corner"; regulator-min-microvolt = <1>; regulator-max-microvolt = <24>; qcom,cpr-fuse-corners = <4>; qcom,cpr-fuse-combos = <1>; qcom,cpr-corners = <23>; qcom,cpr-corner-fmax-map = <7 10 17 23>; qcom,cpr-voltage-ceiling = <632000 632000 632000 632000 632000 632000 632000 700000 700000 700000 828000 828000 828000 828000 828000 828000 828000 1024000 1024000 1024000 1024000 1024000 1024000>; qcom,cpr-voltage-floor = <572000 572000 572000 572000 572000 572000 572000 568000 568000 568000 684000 684000 684000 684000 684000 684000 684000 856000 856000 856000 856000 856000 856000>; qcom,corner-frequencies = <300000000 345600000 422400000 499200000 576000000 633600000 710400000 806400000 883200000 960000000 1036800000 1113600000 1190400000 1248000000 1324800000 1401600000 1478400000 1497600000 1574400000 1651200000 1728000000 1804800000 1881600000>; }; }; }; apc1_cpr: cprh-ctrl@179c4000{ compatible = "qcom,cprh-msmcobalt-kbss-regulator"; reg = <0x179c4000 0x4000>, <0x00784000 0x1000>; reg-names = "cpr_ctrl", "fuse_base"; clocks = <&clock_gcc clk_gcc_hmss_rbcpr_clk>; clock-names = "core_clk"; qcom,cpr-ctrl-name = "apc1"; qcom,cpr-controller-id = <1>; qcom,cpr-sensor-time = <1000>; qcom,cpr-loop-time = <5000000>; qcom,cpr-idle-cycles = <15>; qcom,cpr-up-down-delay-time = <3000>; qcom,cpr-step-quot-init-min = <11>; qcom,cpr-step-quot-init-max = <13>; qcom,cpr-count-mode = <2>; /* Staggered */ qcom,cpr-down-error-step-limit = <1>; qcom,cpr-up-error-step-limit = <1>; qcom,cpr-corner-switch-delay-time = <1600>; qcom,cpr-voltage-settling-time = <1600>; qcom,apm-threshold-voltage = <800000>; qcom,apm-hysteresis-voltage = <4000>; qcom,voltage-step = <4000>; qcom,voltage-base = <352000>; qcom,cpr-saw-use-unit-mV; thread@0 { qcom,cpr-thread-id = <0>; qcom,cpr-consecutive-up = <0>; qcom,cpr-consecutive-down = <2>; qcom,cpr-up-threshold = <0>; qcom,cpr-down-threshold = <2>; apc1_perfcl_vreg: regulator-pwrcl { regulator-name = "apc1_perfcl_corner"; regulator-min-microvolt = <1>; regulator-max-microvolt = <27>; qcom,cpr-fuse-corners = <4>; qcom,cpr-fuse-combos = <1>; qcom,cpr-corners = <26>; qcom,cpr-corner-fmax-map = <8 12 19 26>; qcom,cpr-voltage-ceiling = <632000 632000 632000 632000 632000 632000 632000 632000 700000 700000 700000 700000 828000 828000 828000 828000 828000 828000 828000 1024000 1024000 1024000 1024000 1024000 1024000 1024000>; qcom,cpr-voltage-floor = <572000 572000 572000 572000 572000 572000 572000 572000 568000 568000 568000 568000 684000 684000 684000 684000 684000 684000 684000 856000 856000 856000 856000 856000 856000 856000>; qcom,corner-frequencies = <300000000 345600000 422400000 480000000 556800000 633600000 710400000 787200000 844800000 902400000 979200000 1056000000 1094400000 1171200000 1248000000 1324800000 1401600000 1478400000 1536000000 1632000000 1708800000 1785600000 1862400000 1939200000 2016000000 2092800000>; }; }; }; }; arch/arm/boot/dts/qcom/msmcobalt-rumi.dts +66 −0 Original line number Diff line number Diff line Loading @@ -34,6 +34,72 @@ status = "disabled"; }; &apc0_cpr { qcom,cpr-initial-temp-band = <3>; qcom,cpr-temp-point-map = <0 25 85>; }; &apc0_pwrcl_vreg { qcom,cpr-corner-bands = <4>; qcom,corner-band-allow-core-count-adjustment = <1 1 1 1>; qcom,corner-band-allow-temp-adjustment = <1 0 0 0>; qcom,cpr-corner-band-map = <7 14 18 20>; qcom,max-core-count = <4>; qcom,cpr-corner-band1-temp-core-voltage-adjustment = <(-24000) (-20000) (-20000) (-16000)>, <(-16000) (-16000) (-12000) (-8000)>, <(-8000) (-8000) (-4000) (-4000)>, <0 0 0 0>; qcom,cpr-corner-band2-temp-core-voltage-adjustment = <(-36000) 0 0 0>, <(-32000) 0 0 0>, <(-24000) 0 0 0>, < 0 0 0 0>; qcom,cpr-corner-band3-temp-core-voltage-adjustment = <(-40000) 0 0 0>, <(-36000) 0 0 0>, <(-32000) 0 0 0>, < 0 0 0 0>; qcom,cpr-corner-band4-temp-core-voltage-adjustment = <(-44000) 0 0 0>, <(-32000) 0 0 0>, <(-24000) 0 0 0>, < 0 0 0 0>; }; &apc1_cpr { qcom,cpr-initial-temp-band = <3>; qcom,cpr-temp-point-map = <0 25 85>; }; &apc1_perfcl_vreg { qcom,cpr-corner-bands = <4>; qcom,corner-band-allow-core-count-adjustment = <1 1 1 1>; qcom,corner-band-allow-temp-adjustment = <1 0 0 0>; qcom,cpr-corner-band-map = <6 12 15 20>; qcom,max-core-count = <4>; qcom,cpr-corner-band1-temp-core-voltage-adjustment = <(-24000) (-20000) (-20000) (-16000)>, <(-16000) (-16000) (-12000) (-8000)>, <(-8000) (-8000) (-4000) (-4000)>, <0 0 0 0>; qcom,cpr-corner-band2-temp-core-voltage-adjustment = <(-36000) 0 0 0>, <(-32000) 0 0 0>, <(-24000) 0 0 0>, < 0 0 0 0>; qcom,cpr-corner-band3-temp-core-voltage-adjustment = <(-40000) 0 0 0>, <(-36000) 0 0 0>, <(-32000) 0 0 0>, < 0 0 0 0>; qcom,cpr-corner-band4-temp-core-voltage-adjustment = <(-44000) 0 0 0>, <(-32000) 0 0 0>, <(-24000) 0 0 0>, < 0 0 0 0>; }; &qusb_phy0 { reg = <0x0a928000 0x8000>, <0x0a8f8800 0x400>, Loading arch/arm64/configs/msmcortex-perf_defconfig +1 −0 Original line number Diff line number Diff line Loading @@ -355,6 +355,7 @@ CONFIG_REGULATOR_CPR=y CONFIG_REGULATOR_CPR3_HMSS=y CONFIG_REGULATOR_CPR3_MMSS=y CONFIG_REGULATOR_CPR4_APSS=y CONFIG_REGULATOR_CPRH_KBSS=y CONFIG_REGULATOR_KRYO=y CONFIG_MEDIA_SUPPORT=y CONFIG_MEDIA_CAMERA_SUPPORT=y Loading Loading
Documentation/devicetree/bindings/arm/msm/qcom,osm.txt 0 → 100644 +359 −0 Original line number Diff line number Diff line Qualcomm Technologies, Inc. OSM Bindings Operating State Manager (OSM) is a hardware engine used by some Qualcomm Technologies, Inc. (QTI) SoCs to manage frequency and voltage scaling in hardware. OSM is capable of controlling frequency and voltage requests for multiple clusters via the existence of multiple OSM domains. Properties: - compatible Usage: required Value type: <string> Definition: must be "qcom,cpu-clock-osm". - reg Usage: required Value type: <prop-encoded-array> Definition: Addresses and sizes for the memory of the OSM controller and cluster PLL management. - reg-names Usage: required Value type: <stringlist> Definition: Address names. Must be "osm", "pwrcl_pll", and "perfcl_pll." Must be specified in the same order as the corresponding addresses are specified in the reg property. - vdd-pwrcl-supply Usage: required Value type: <phandle> Definition: phandle of the underlying regulator device that manages the voltage supply of the Power cluster. - vdd-perfcl-supply Usage: required Value type: <phandle> Definition: phandle of the underlying regulator device that manages the voltage supply of the Performance cluster. - interrupts Usage: required Value type: <prop-encoded-array> Definition: OSM interrupt specifier. - interrupt-names Usage: required Value type: <stringlist> Definition: Interrupt names. this list must match up 1-to-1 with the interrupts specified in the 'interrupts' property. "pwrcl-irq" and "perfcl-irq" must be specified. - qcom,pwrcl-speedbinX-v0 Usage: required Value type: <prop-encoded-array> Definition: Array which defines the frequency in Hertz, frequency, and PLL override data used by the OSM hardware for each supported DCVS setpoint of the Power cluster. - qcom,perfcl-speedbinX-v0 Usage: required Value type: <prop-encoded-array> Definition: Array which defines the frequency in Hertz, frequency, and PLL override data used by the OSM hardware for each supported DCVS setpoint of the Performance cluster. - qcom,osm-no-tz Usage: optional Value type: <empty> Definition: Boolean flag which indicates that there is no programming of the OSM hardware performed by the secure world. - qcom,osm-pll-setup Usage: optional Value type: <empty> Definition: Boolean flag which indicates that the PLL setup sequence must be executed for each clock domain managed by the OSM controller. - qcom,up-timer Usage: optional Value type: <prop-encoded-array> Definition: Array which defines the DCVS up timer value in microseconds for each of the two clusters managed by the OSM controller. - qcom,down-timer Usage: optional Value type: <prop-encoded-array> Definition: Array which defines the DCVS down timer value in microseconds for each of the two clusters managed by the OSM controller. - qcom,pc-override-index Usage: optional Value type: <prop-encoded-array> Definition: Array which defines the OSM performance index to be used when each cluster enters certain low power modes. - qcom,set-ret-inactive Usage: optional Value type: <empty> Definition: Boolean flag which indicates if domains in retention must be treated as inactive. - qcom,enable-llm-freq-vote Usage: optional Value type: <empty> Definition: Boolean flag which indicates if Limits hardware frequency votes must be honored by OSM. - qcom,llm-freq-up-timer Usage: optional Value type: <prop-encoded-array> Definition: Array which devines the LLM frequency up timer value in microseconds for each of the two clusters managed by the OSM controller. - qcom,llm-freq-down-timer Usage: optional Value type: <prop-encoded-array> Definition: Array which devines the LLM frequency down timer value in microseconds for each of the two clusters managed by the OSM controller. - qcom,enable-llm-volt-vote Usage: optional Value type: <empty> Definition: Boolean flag which indicates if Limits hardware voltage votes must be honored by OSM. - qcom,llm-volt-up-timer Usage: optional Value type: <prop-encoded-array> Definition: Array which devines the LLM voltage up timer value in microseconds for each of the two clusters managed by the OSM controller. - qcom,llm-volt-down-timer Usage: optional Value type: <prop-encoded-array> Definition: Array which devines the LLM voltage down timer value in microseconds for each of the two clusters managed by the OSM controller. - qcom,cc-reads Usage: optional Value type: <integer> Definition: Defines the number of times the cycle counters must be read to determine the performance level of each clock domain. - qcom,l-val-base Usage: required Value type: <prop-encoded-array> Definition: Array which defines the register addresses of the L_VAL control register for each of the two clusters managed by the OSM controller. - qcom,apcs-itm-present Usage: required Value type: <prop-encoded-array> Definition: Array which defines the register addresses of the ITM control register for each of the two clusters managed by the OSM controller. - qcom,apcs-pll-user-ctl Usage: required Value type: <prop-encoded-array> Definition: Array which defines the register addresses of the PLL user control register for each of the two clusters managed by the OSM controller. - qcom,apcs-cfg-rcgr Usage: required Value type: <prop-encoded-array> Definition: Array which defines the register addresses of the RCGR configuration register for each of the two clusters managed by the OSM controller. - qcom,apcs-cmd-rcgr Usage: required Value type: <prop-encoded-array> Definition: Array which defines the register addresses of the RCGR command register for each of the two clusters managed by the OSM controller. - qcom,apm-mode-ctl Usage: required Value type: <prop-encoded-array> Definition: Array which defines the register addresses of the APM control register for each of the two clusters managed by the OSM controller. - qcom,apm-ctrl-status Usage: required Value type: <prop-encoded-array> Definition: Array which defines the register addresses of the APM controller status register for each of the two clusters managed by the OSM controller. - qcom,red-fsm-en Usage: optional Value type: <empty> Definition: Boolean flag which indicates if the reduction FSM should be enabled. - qcom,boost-fsm-en Usage: optional Value type: <empty> Definition: Boolean flag which indicates if the boost FSM should be enabled. - qcom,safe-fsm-en Usage: optional Value type: <empty> Definition: Boolean flag which indicates if the safe FSM should be enabled. - qcom,ps-fsm-en Usage: optional Value type: <empty> Definition: Boolean flag which indicates if the PS FSM should be enabled. - qcom,droop-fsm-en Usage: optional Value type: <empty> Definition: Boolean flag which indicates if the droop FSM should be enabled. - qcom,wfx-fsm-en Usage: optional Value type: <empty> Definition: Boolean flag which indicates if the WFX FSM should be enabled. - qcom,pc-fsm-en Usage: optional Value type: <empty> Definition: Boolean flag which indicates if the PC/RET FSM should be enabled. - clock-names Usage: required Value type: <string> Definition: Must be "aux_clk". - clocks Usage: required Value type: <phandle> Definition: Phandle to the aux clock device. Example: clock_cpu: qcom,cpu-clock-cobalt@179c0000 { compatible = "qcom,cpu-clock-osm"; reg = <0x179C0000 0x4000>, <0x17916000 0x1000>, <0x17816000 0x1000>; reg-names = "osm", "pwrcl_pll", "perfcl_pll"; vdd-pwrcl-supply = <&apc0_pwrcl_vreg>; vdd-perfcl-supply = <&apc1_perfcl_vreg>; interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>; interrupt-names = "pwrcl-irq", "perfcl-irq"; qcom,pwrcl-speedbin0-v0 = < 300000000 0x4000f 0x31e001e >, < 345600000 0x5040012 0x4200020 >, < 422400000 0x5040016 0x4200020 >, < 499200000 0x504001a 0x5200020 >, < 576000000 0x504001e 0x6200020 >, < 633600000 0x4040021 0x7200020 >, < 710400000 0x4040025 0x7200020 >, < 806400000 0x404002a 0x8220022 >, < 883200000 0x404002e 0x9250025 >, < 960000000 0x4040032 0xa280028 >, < 1036800000 0x4040036 0xb2b002b >, < 1113600000 0x404003a 0xc2e002e >, < 1190400000 0x404003e 0xc320032 >, < 1248000000 0x4040041 0xd340034 >, < 1324800000 0x4040045 0xe370037 >, < 1401600000 0x4040049 0xf3a003a >, < 1478400000 0x404004d 0x103e003e >, < 1497600000 0x404004e 0x103e003e >, < 1574400000 0x4040052 0x10420042 >, < 1651200000 0x4040056 0x11450045 >, < 1728000000 0x404005a 0x12480048 >, < 1804800000 0x404005e 0x134b004b >, < 1881600000 0x4040062 0x144e004e >; qcom,perfcl-speedbin0-v0 = < 300000000 0x4000f 0x3200020 >, < 345600000 0x5040012 0x4200020 >, < 422400000 0x5040016 0x4200020 >, < 480000000 0x5040019 0x5200020 >, < 556800000 0x504001d 0x6200020 >, < 633600000 0x4040021 0x7200020 >, < 710400000 0x4040025 0x7200020 >, < 787200000 0x4040029 0x8210021 >, < 844800000 0x404002c 0x9240024 >, < 902400000 0x404002f 0x9260026 >, < 979200000 0x4040033 0xa290029 >, < 1056000000 0x4040037 0xb2c002c >, < 1094400000 0x4040039 0xb2e002e >, < 1171200000 0x404003d 0xc300030 >, < 1248000000 0x4040041 0xd340034 >, < 1324800000 0x4040045 0xe370037 >, < 1401600000 0x4040049 0xf3b003b >, < 1478400000 0x404004d 0xf3e003e >, < 1536000000 0x4040050 0x10400040 >, < 1632000000 0x4040055 0x11440044 >, < 1708800000 0x4040059 0x12480048 >, < 1785600000 0x404005d 0x134a004a >, < 1862400000 0x4040061 0x134e004e >, < 1939200000 0x4040065 0x14510051 >, < 2016000000 0x4040069 0x15540054 >, < 2092800000 0x404006d 0x16570057 >; qcom,osm-no-tz; qcom,osm-pll-setup; qcom,up-timer = <1 1>; qcom,down-timer = <1 1>; qcom,pc-override-index = <0 0>; qcom,set-ret-inactive; qcom,enable-llm-freq-vote; qcom,llm-freq-up-timer = <1 1>; qcom,llm-freq-down-timer = <1 1>; qcom,enable-llm-volt-vote; qcom,llm-volt-up-timer = <1 1>; qcom,llm-volt-down-timer = <1 1>; qcom,cc-reads = <10>; qcom,l-val-base = <0x17916004 0x17816004>; qcom,apcs-itm-present = <0x179d143c 0x179d143c>; qcom,apcs-pll-user-ctl = <0x1791600c 0x1781600c>; qcom,apcs-cfg-rcgr = <0x17911054 0x17811054>; qcom,apcs-cmd-rcgr = <0x17911050 0x17811050>; qcom,apm-mode-ctl = <0x179d0004 0x179d0010>; qcom,apm-ctrl-status = <0x179d000c 0x179d0018>; clock-names = "aux_clk"; clocks = <&clock_gcc clk_gpll0_ao>; #clock-cells = <1>; }; }
Documentation/devicetree/bindings/regulator/cprh-kbss-regulator.txt 0 → 100644 +411 −0 File added.Preview size limit exceeded, changes collapsed. Show changes
arch/arm/boot/dts/qcom/msmcobalt-regulator.dtsi +149 −0 Original line number Diff line number Diff line Loading @@ -528,3 +528,152 @@ }; }; &soc { /* CPR controller regulators */ apc0_cpr: cprh-ctrl@179c8000 { compatible = "qcom,cprh-msmcobalt-kbss-regulator"; reg = <0x179c8000 0x4000>, <0x00784000 0x1000>; reg-names = "cpr_ctrl", "fuse_base"; clocks = <&clock_gcc clk_gcc_hmss_rbcpr_clk>; clock-names = "core_clk"; qcom,cpr-ctrl-name = "apc0"; qcom,cpr-controller-id = <0>; qcom,cpr-sensor-time = <1000>; qcom,cpr-loop-time = <5000000>; qcom,cpr-idle-cycles = <15>; qcom,cpr-up-down-delay-time = <3000>; qcom,cpr-step-quot-init-min = <11>; qcom,cpr-step-quot-init-max = <13>; qcom,cpr-count-mode = <2>; /* Staggered */ qcom,cpr-down-error-step-limit = <1>; qcom,cpr-up-error-step-limit = <1>; qcom,cpr-corner-switch-delay-time = <1600>; qcom,cpr-voltage-settling-time = <1600>; qcom,apm-threshold-voltage = <800000>; qcom,apm-hysteresis-voltage = <4000>; qcom,voltage-step = <4000>; qcom,voltage-base = <352000>; qcom,cpr-saw-use-unit-mV; thread@0 { qcom,cpr-thread-id = <0>; qcom,cpr-consecutive-up = <0>; qcom,cpr-consecutive-down = <2>; qcom,cpr-up-threshold = <0>; qcom,cpr-down-threshold = <2>; apc0_pwrcl_vreg: regulator-pwrcl { regulator-name = "apc0_pwrcl_corner"; regulator-min-microvolt = <1>; regulator-max-microvolt = <24>; qcom,cpr-fuse-corners = <4>; qcom,cpr-fuse-combos = <1>; qcom,cpr-corners = <23>; qcom,cpr-corner-fmax-map = <7 10 17 23>; qcom,cpr-voltage-ceiling = <632000 632000 632000 632000 632000 632000 632000 700000 700000 700000 828000 828000 828000 828000 828000 828000 828000 1024000 1024000 1024000 1024000 1024000 1024000>; qcom,cpr-voltage-floor = <572000 572000 572000 572000 572000 572000 572000 568000 568000 568000 684000 684000 684000 684000 684000 684000 684000 856000 856000 856000 856000 856000 856000>; qcom,corner-frequencies = <300000000 345600000 422400000 499200000 576000000 633600000 710400000 806400000 883200000 960000000 1036800000 1113600000 1190400000 1248000000 1324800000 1401600000 1478400000 1497600000 1574400000 1651200000 1728000000 1804800000 1881600000>; }; }; }; apc1_cpr: cprh-ctrl@179c4000{ compatible = "qcom,cprh-msmcobalt-kbss-regulator"; reg = <0x179c4000 0x4000>, <0x00784000 0x1000>; reg-names = "cpr_ctrl", "fuse_base"; clocks = <&clock_gcc clk_gcc_hmss_rbcpr_clk>; clock-names = "core_clk"; qcom,cpr-ctrl-name = "apc1"; qcom,cpr-controller-id = <1>; qcom,cpr-sensor-time = <1000>; qcom,cpr-loop-time = <5000000>; qcom,cpr-idle-cycles = <15>; qcom,cpr-up-down-delay-time = <3000>; qcom,cpr-step-quot-init-min = <11>; qcom,cpr-step-quot-init-max = <13>; qcom,cpr-count-mode = <2>; /* Staggered */ qcom,cpr-down-error-step-limit = <1>; qcom,cpr-up-error-step-limit = <1>; qcom,cpr-corner-switch-delay-time = <1600>; qcom,cpr-voltage-settling-time = <1600>; qcom,apm-threshold-voltage = <800000>; qcom,apm-hysteresis-voltage = <4000>; qcom,voltage-step = <4000>; qcom,voltage-base = <352000>; qcom,cpr-saw-use-unit-mV; thread@0 { qcom,cpr-thread-id = <0>; qcom,cpr-consecutive-up = <0>; qcom,cpr-consecutive-down = <2>; qcom,cpr-up-threshold = <0>; qcom,cpr-down-threshold = <2>; apc1_perfcl_vreg: regulator-pwrcl { regulator-name = "apc1_perfcl_corner"; regulator-min-microvolt = <1>; regulator-max-microvolt = <27>; qcom,cpr-fuse-corners = <4>; qcom,cpr-fuse-combos = <1>; qcom,cpr-corners = <26>; qcom,cpr-corner-fmax-map = <8 12 19 26>; qcom,cpr-voltage-ceiling = <632000 632000 632000 632000 632000 632000 632000 632000 700000 700000 700000 700000 828000 828000 828000 828000 828000 828000 828000 1024000 1024000 1024000 1024000 1024000 1024000 1024000>; qcom,cpr-voltage-floor = <572000 572000 572000 572000 572000 572000 572000 572000 568000 568000 568000 568000 684000 684000 684000 684000 684000 684000 684000 856000 856000 856000 856000 856000 856000 856000>; qcom,corner-frequencies = <300000000 345600000 422400000 480000000 556800000 633600000 710400000 787200000 844800000 902400000 979200000 1056000000 1094400000 1171200000 1248000000 1324800000 1401600000 1478400000 1536000000 1632000000 1708800000 1785600000 1862400000 1939200000 2016000000 2092800000>; }; }; }; };
arch/arm/boot/dts/qcom/msmcobalt-rumi.dts +66 −0 Original line number Diff line number Diff line Loading @@ -34,6 +34,72 @@ status = "disabled"; }; &apc0_cpr { qcom,cpr-initial-temp-band = <3>; qcom,cpr-temp-point-map = <0 25 85>; }; &apc0_pwrcl_vreg { qcom,cpr-corner-bands = <4>; qcom,corner-band-allow-core-count-adjustment = <1 1 1 1>; qcom,corner-band-allow-temp-adjustment = <1 0 0 0>; qcom,cpr-corner-band-map = <7 14 18 20>; qcom,max-core-count = <4>; qcom,cpr-corner-band1-temp-core-voltage-adjustment = <(-24000) (-20000) (-20000) (-16000)>, <(-16000) (-16000) (-12000) (-8000)>, <(-8000) (-8000) (-4000) (-4000)>, <0 0 0 0>; qcom,cpr-corner-band2-temp-core-voltage-adjustment = <(-36000) 0 0 0>, <(-32000) 0 0 0>, <(-24000) 0 0 0>, < 0 0 0 0>; qcom,cpr-corner-band3-temp-core-voltage-adjustment = <(-40000) 0 0 0>, <(-36000) 0 0 0>, <(-32000) 0 0 0>, < 0 0 0 0>; qcom,cpr-corner-band4-temp-core-voltage-adjustment = <(-44000) 0 0 0>, <(-32000) 0 0 0>, <(-24000) 0 0 0>, < 0 0 0 0>; }; &apc1_cpr { qcom,cpr-initial-temp-band = <3>; qcom,cpr-temp-point-map = <0 25 85>; }; &apc1_perfcl_vreg { qcom,cpr-corner-bands = <4>; qcom,corner-band-allow-core-count-adjustment = <1 1 1 1>; qcom,corner-band-allow-temp-adjustment = <1 0 0 0>; qcom,cpr-corner-band-map = <6 12 15 20>; qcom,max-core-count = <4>; qcom,cpr-corner-band1-temp-core-voltage-adjustment = <(-24000) (-20000) (-20000) (-16000)>, <(-16000) (-16000) (-12000) (-8000)>, <(-8000) (-8000) (-4000) (-4000)>, <0 0 0 0>; qcom,cpr-corner-band2-temp-core-voltage-adjustment = <(-36000) 0 0 0>, <(-32000) 0 0 0>, <(-24000) 0 0 0>, < 0 0 0 0>; qcom,cpr-corner-band3-temp-core-voltage-adjustment = <(-40000) 0 0 0>, <(-36000) 0 0 0>, <(-32000) 0 0 0>, < 0 0 0 0>; qcom,cpr-corner-band4-temp-core-voltage-adjustment = <(-44000) 0 0 0>, <(-32000) 0 0 0>, <(-24000) 0 0 0>, < 0 0 0 0>; }; &qusb_phy0 { reg = <0x0a928000 0x8000>, <0x0a8f8800 0x400>, Loading
arch/arm64/configs/msmcortex-perf_defconfig +1 −0 Original line number Diff line number Diff line Loading @@ -355,6 +355,7 @@ CONFIG_REGULATOR_CPR=y CONFIG_REGULATOR_CPR3_HMSS=y CONFIG_REGULATOR_CPR3_MMSS=y CONFIG_REGULATOR_CPR4_APSS=y CONFIG_REGULATOR_CPRH_KBSS=y CONFIG_REGULATOR_KRYO=y CONFIG_MEDIA_SUPPORT=y CONFIG_MEDIA_CAMERA_SUPPORT=y Loading
