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Commit e9a0a3ad authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-fixes-3.10' of git://people.freedesktop.org/~agd5f/linux into drm-next 

just a few minor fixes for radeon.

* 'drm-fixes-3.10' of git://people.freedesktop.org/~agd5f/linux:
  radeon: use max_bus_speed to activate gen2 speeds
  drm/radeon: narrow scope of Apple re-POST hack
  drm/radeon: don't check crtcs in card_posted() on cards without DCE
  drm/radeon: fix card_posted check for newer asics
  drm/radeon: fix typo in cu_per_sh on verde
  drm/radeon: UVD block on SUMO2 is the same as on SUMO
parents c89b65e7 7e0e4196

drivers/gpu/drm/radeon/evergreen.c

+3 −7
Original line number Diff line number Diff line
@@ -4999,8 +4999,7 @@ void evergreen_fini(struct radeon_device *rdev) 


void evergreen_pcie_gen2_enable(struct radeon_device *rdev)

{

	u32 link_width_cntl, speed_cntl, mask;

	int ret;

	u32 link_width_cntl, speed_cntl;



	if (radeon_pcie_gen2 == 0)

		return;
@@ -5015,11 +5014,8 @@ void evergreen_pcie_gen2_enable(struct radeon_device *rdev) 
	if (ASIC_IS_X2(rdev))

		return;



	ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);

	if (ret != 0)

		return;



	if (!(mask & DRM_PCIE_SPEED_50))

	if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&

		(rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))

		return;



	speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);

drivers/gpu/drm/radeon/r600.c

+2 −7
Original line number Diff line number Diff line
@@ -4631,8 +4631,6 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev) 
{

	u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;

	u16 link_cntl2;

	u32 mask;

	int ret;



	if (radeon_pcie_gen2 == 0)

		return;
@@ -4651,11 +4649,8 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev) 
	if (rdev->family <= CHIP_R600)

		return;



	ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);

	if (ret != 0)

		return;



	if (!(mask & DRM_PCIE_SPEED_50))

	if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&

		(rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))

		return;



	speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);

drivers/gpu/drm/radeon/radeon_device.c

+16 −11
Original line number Diff line number Diff line
@@ -467,23 +467,27 @@ bool radeon_card_posted(struct radeon_device *rdev) 
{

	uint32_t reg;



	/* required for EFI mode on macbook2,1 which uses an r5xx asic */

	if (efi_enabled(EFI_BOOT) &&

	    rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE)

	    (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&

	    (rdev->family < CHIP_R600))

		return false;



	if (ASIC_IS_NODCE(rdev))

		goto check_memsize;



	/* first check CRTCs */

	if (ASIC_IS_DCE41(rdev)) {

	if (ASIC_IS_DCE4(rdev)) {

		reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |

			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);

		if (reg & EVERGREEN_CRTC_MASTER_EN)

			return true;

	} else if (ASIC_IS_DCE4(rdev)) {

		reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |

			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |

			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |

			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |

			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |

			if (rdev->num_crtc >= 4) {

				reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |

					RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);

			}

			if (rdev->num_crtc >= 6) {

				reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |

					RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);

			}

		if (reg & EVERGREEN_CRTC_MASTER_EN)

			return true;

	} else if (ASIC_IS_AVIVO(rdev)) {
@@ -500,6 +504,7 @@ bool radeon_card_posted(struct radeon_device *rdev) 
		}

	}



check_memsize:

	/* then check MEM_SIZE, in case the crtcs are off */

	if (rdev->family >= CHIP_R600)

		reg = RREG32(R600_CONFIG_MEMSIZE);

drivers/gpu/drm/radeon/rv770.c

+3 −10
Original line number Diff line number Diff line
@@ -862,10 +862,8 @@ int rv770_uvd_resume(struct radeon_device *rdev) 
		chip_id = 0x0100000b;

		break;

	case CHIP_SUMO:

		chip_id = 0x0100000c;

		break;

	case CHIP_SUMO2:

		chip_id = 0x0100000d;

		chip_id = 0x0100000c;

		break;

	case CHIP_PALM:

		chip_id = 0x0100000e;
@@ -2113,8 +2111,6 @@ static void rv770_pcie_gen2_enable(struct radeon_device *rdev) 
{

	u32 link_width_cntl, lanes, speed_cntl, tmp;

	u16 link_cntl2;

	u32 mask;

	int ret;



	if (radeon_pcie_gen2 == 0)

		return;
@@ -2129,11 +2125,8 @@ static void rv770_pcie_gen2_enable(struct radeon_device *rdev) 
	if (ASIC_IS_X2(rdev))

		return;



	ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);

	if (ret != 0)

		return;



	if (!(mask & DRM_PCIE_SPEED_50))

	if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&

		(rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))

		return;



	DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");

drivers/gpu/drm/radeon/si.c

+1 −1
Original line number Diff line number Diff line
@@ -2616,7 +2616,7 @@ static void si_gpu_init(struct radeon_device *rdev) 
	default:

		rdev->config.si.max_shader_engines = 1;

		rdev->config.si.max_tile_pipes = 4;

		rdev->config.si.max_cu_per_sh = 2;

		rdev->config.si.max_cu_per_sh = 5;

		rdev->config.si.max_sh_per_se = 2;

		rdev->config.si.max_backends_per_se = 4;

		rdev->config.si.max_texture_channel_caches = 4;