clk: msm: mdss: add HDMI PLL sequence for external 1.8V supply (e98d085b) · Commits · e / devices / android_kernel_xiaomi_markw

Documentation/devicetree/bindings/fb/mdss-pll.txt

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -14,7 +14,7 @@ Required properties:
	"qcom,mdss_dsi_pll_8996", "qcom,mdss_hdmi_pll_8996",		"qcom,mdss_dsi_pll_8996", "qcom,mdss_hdmi_pll_8996",
	"qcom,mdss_hdmi_pll_8996_v2", "qcom,mdss_dsi_pll_8996_v2",		"qcom,mdss_hdmi_pll_8996_v2", "qcom,mdss_dsi_pll_8996_v2",
	"qcom,mdss_hdmi_pll_8996_v3", "qcom,mdss_dsi_pll_8952",		"qcom,mdss_hdmi_pll_8996_v3", "qcom,mdss_dsi_pll_8952",
	"qcom,mdss_dsi_pll_8937"		"qcom,mdss_dsi_pll_8937", "qcom,mdss_hdmi_pll_8996_v3_1p8"
	- cell-index: Specifies the controller used		- cell-index: Specifies the controller used
	- reg: offset and length of the register set for the device.		- reg: offset and length of the register set for the device.
	- reg-names : names to refer to register sets related to this device		- reg-names : names to refer to register sets related to this device

drivers/clk/msm/mdss/mdss-hdmi-pll-8996.c

+87 −18

Original line number	Original line	Diff line number	Diff line
	@@ -35,6 +35,7 @@
	#define HDMI_VERSION_8996_V1 1		#define HDMI_VERSION_8996_V1 1
	#define HDMI_VERSION_8996_V2 2		#define HDMI_VERSION_8996_V2 2
	#define HDMI_VERSION_8996_V3 3		#define HDMI_VERSION_8996_V3 3
			#define HDMI_VERSION_8996_V3_1_8 4

	#define HDMI_VCO_MAX_FREQ 12000000000		#define HDMI_VCO_MAX_FREQ 12000000000
	#define HDMI_VCO_MIN_FREQ 8000000000		#define HDMI_VCO_MIN_FREQ 8000000000
	@@ -1544,6 +1545,7 @@ static int hdmi_8996_calculate(u32 pix_clk,
	{		{
	switch (ver) {		switch (ver) {
	case HDMI_VERSION_8996_V3:		case HDMI_VERSION_8996_V3:
			case HDMI_VERSION_8996_V3_1_8:
	return hdmi_8996_v3_calculate(pix_clk, cfg);		return hdmi_8996_v3_calculate(pix_clk, cfg);
	case HDMI_VERSION_8996_V2:		case HDMI_VERSION_8996_V2:
	return hdmi_8996_v2_calculate(pix_clk, cfg);		return hdmi_8996_v2_calculate(pix_clk, cfg);
	@@ -1574,6 +1576,7 @@ static int hdmi_8996_phy_pll_set_clk_rate(struct clk *c, u32 tmds_clk, u32 ver)
	switch (ver) {		switch (ver) {
	case HDMI_VERSION_8996_V2:		case HDMI_VERSION_8996_V2:
	case HDMI_VERSION_8996_V3:		case HDMI_VERSION_8996_V3:
			case HDMI_VERSION_8996_V3_1_8:
	MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_BG_CTRL, 0x04);		MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_BG_CTRL, 0x04);
	break;		break;
	};		};
	@@ -1680,34 +1683,58 @@ static int hdmi_8996_phy_pll_set_clk_rate(struct clk *c, u32 tmds_clk, u32 ver)
	cfg.com_coreclk_div);		cfg.com_coreclk_div);
	MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_CMN_CONFIG, 0x02);		MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_CMN_CONFIG, 0x02);

	if (ver == HDMI_VERSION_8996_V3)		if (ver == HDMI_VERSION_8996_V3 \|\| ver == HDMI_VERSION_8996_V3_1_8)
	MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_RESCODE_DIV_NUM, 0x15);		MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_RESCODE_DIV_NUM, 0x15);

	/* TX lanes setup (TX 0/1/2/3) */		/* TX lanes setup (TX 0/1/2/3) */
			if (ver == HDMI_VERSION_8996_V3_1_8) {
			MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET,
			QSERDES_TX_L0_TX_DRV_LVL,
			0x00000023);
			} else {
	MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET,		MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET,
	QSERDES_TX_L0_TX_DRV_LVL,		QSERDES_TX_L0_TX_DRV_LVL,
	cfg.tx_l0_tx_drv_lvl);		cfg.tx_l0_tx_drv_lvl);
			}
	MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET,		MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET,
	QSERDES_TX_L0_TX_EMP_POST1_LVL,		QSERDES_TX_L0_TX_EMP_POST1_LVL,
	cfg.tx_l0_tx_emp_post1_lvl);		cfg.tx_l0_tx_emp_post1_lvl);

			if (ver == HDMI_VERSION_8996_V3_1_8) {
			MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L1_BASE_OFFSET,
			QSERDES_TX_L0_TX_DRV_LVL,
			0x00000023);
			} else {
	MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L1_BASE_OFFSET,		MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L1_BASE_OFFSET,
	QSERDES_TX_L0_TX_DRV_LVL,		QSERDES_TX_L0_TX_DRV_LVL,
	cfg.tx_l1_tx_drv_lvl);		cfg.tx_l1_tx_drv_lvl);
			}
	MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L1_BASE_OFFSET,		MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L1_BASE_OFFSET,
	QSERDES_TX_L0_TX_EMP_POST1_LVL,		QSERDES_TX_L0_TX_EMP_POST1_LVL,
	cfg.tx_l1_tx_emp_post1_lvl);		cfg.tx_l1_tx_emp_post1_lvl);

			if (ver == HDMI_VERSION_8996_V3_1_8) {
			MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET,
			QSERDES_TX_L0_TX_DRV_LVL,
			0x00000023);
			} else {
	MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET,		MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET,
	QSERDES_TX_L0_TX_DRV_LVL,		QSERDES_TX_L0_TX_DRV_LVL,
	cfg.tx_l2_tx_drv_lvl);		cfg.tx_l2_tx_drv_lvl);
			}
	MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET,		MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET,
	QSERDES_TX_L0_TX_EMP_POST1_LVL,		QSERDES_TX_L0_TX_EMP_POST1_LVL,
	cfg.tx_l2_tx_emp_post1_lvl);		cfg.tx_l2_tx_emp_post1_lvl);

			if (ver == HDMI_VERSION_8996_V3_1_8) {
			MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET,
			QSERDES_TX_L0_TX_DRV_LVL,
			0x00000020);
			} else {
	MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET,		MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET,
	QSERDES_TX_L0_TX_DRV_LVL,		QSERDES_TX_L0_TX_DRV_LVL,
	cfg.tx_l3_tx_drv_lvl);		cfg.tx_l3_tx_drv_lvl);
			}
	MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET,		MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET,
	QSERDES_TX_L0_TX_EMP_POST1_LVL,		QSERDES_TX_L0_TX_EMP_POST1_LVL,
	cfg.tx_l3_tx_emp_post1_lvl);		cfg.tx_l3_tx_emp_post1_lvl);
	@@ -1736,9 +1763,15 @@ static int hdmi_8996_phy_pll_set_clk_rate(struct clk *c, u32 tmds_clk, u32 ver)
	MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET,		MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET,
	QSERDES_TX_L0_VMODE_CTRL1,		QSERDES_TX_L0_VMODE_CTRL1,
	cfg.tx_l3_vmode_ctrl1);		cfg.tx_l3_vmode_ctrl1);
			if (ver == HDMI_VERSION_8996_V3_1_8) {
			MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET,
			QSERDES_TX_L0_VMODE_CTRL2,
			0x0000000D);
			} else {
	MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET,		MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET,
	QSERDES_TX_L0_VMODE_CTRL2,		QSERDES_TX_L0_VMODE_CTRL2,
	cfg.tx_l3_vmode_ctrl2);		cfg.tx_l3_vmode_ctrl2);
			}

	MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET,		MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET,
	QSERDES_TX_L0_TX_DRV_LVL_OFFSET, 0x00);		QSERDES_TX_L0_TX_DRV_LVL_OFFSET, 0x00);
	@@ -2153,6 +2186,11 @@ static int hdmi_8996_v3_vco_enable(struct clk *c)
	return hdmi_8996_vco_enable(c, HDMI_VERSION_8996_V3);		return hdmi_8996_vco_enable(c, HDMI_VERSION_8996_V3);
	}		}

			static int hdmi_8996_v3_1p8_vco_enable(struct clk *c)
			{
			return hdmi_8996_vco_enable(c, HDMI_VERSION_8996_V3_1_8);
			}

	static int hdmi_8996_vco_set_rate(struct clk *c, unsigned long rate, u32 ver)		static int hdmi_8996_vco_set_rate(struct clk *c, unsigned long rate, u32 ver)
	{		{
	struct hdmi_pll_vco_clk *vco = to_hdmi_8996_vco_clk(c);		struct hdmi_pll_vco_clk *vco = to_hdmi_8996_vco_clk(c);
	@@ -2206,6 +2244,11 @@ static int hdmi_8996_v3_vco_set_rate(struct clk *c, unsigned long rate)
	return hdmi_8996_vco_set_rate(c, rate, HDMI_VERSION_8996_V3);		return hdmi_8996_vco_set_rate(c, rate, HDMI_VERSION_8996_V3);
	}		}

			static int hdmi_8996_v3_1p8_vco_set_rate(struct clk *c, unsigned long rate)
			{
			return hdmi_8996_vco_set_rate(c, rate, HDMI_VERSION_8996_V3_1_8);
			}

	static unsigned long hdmi_8996_vco_get_rate(struct clk *c)		static unsigned long hdmi_8996_vco_get_rate(struct clk *c)
	{		{
	unsigned long freq = 0;		unsigned long freq = 0;
	@@ -2257,6 +2300,11 @@ static int hdmi_8996_v3_vco_prepare(struct clk *c)
	return hdmi_8996_vco_prepare(c, HDMI_VERSION_8996_V3);		return hdmi_8996_vco_prepare(c, HDMI_VERSION_8996_V3);
	}		}

			static int hdmi_8996_v3_1p8_vco_prepare(struct clk *c)
			{
			return hdmi_8996_vco_prepare(c, HDMI_VERSION_8996_V3_1_8);
			}

	static void hdmi_8996_vco_unprepare(struct clk *c)		static void hdmi_8996_vco_unprepare(struct clk *c)
	{		{
	struct hdmi_pll_vco_clk *vco = to_hdmi_8996_vco_clk(c);		struct hdmi_pll_vco_clk *vco = to_hdmi_8996_vco_clk(c);
	@@ -2346,6 +2394,17 @@ static struct clk_ops hdmi_8996_v3_vco_clk_ops = {
	.handoff = hdmi_8996_vco_handoff,		.handoff = hdmi_8996_vco_handoff,
	};		};

			static struct clk_ops hdmi_8996_v3_1p8_vco_clk_ops = {
			.enable = hdmi_8996_v3_1p8_vco_enable,
			.set_rate = hdmi_8996_v3_1p8_vco_set_rate,
			.get_rate = hdmi_8996_vco_get_rate,
			.round_rate = hdmi_8996_vco_round_rate,
			.prepare = hdmi_8996_v3_1p8_vco_prepare,
			.unprepare = hdmi_8996_vco_unprepare,
			.handoff = hdmi_8996_vco_handoff,
			};


	static struct hdmi_pll_vco_clk hdmi_vco_clk = {		static struct hdmi_pll_vco_clk hdmi_vco_clk = {
	.c = {		.c = {
	.dbg_name = "hdmi_8996_vco_clk",		.dbg_name = "hdmi_8996_vco_clk",
	@@ -2377,6 +2436,9 @@ int hdmi_8996_pll_clock_register(struct platform_device *pdev,
	case HDMI_VERSION_8996_V3:		case HDMI_VERSION_8996_V3:
	hdmi_vco_clk.c.ops = &hdmi_8996_v3_vco_clk_ops;		hdmi_vco_clk.c.ops = &hdmi_8996_v3_vco_clk_ops;
	break;		break;
			case HDMI_VERSION_8996_V3_1_8:
			hdmi_vco_clk.c.ops = &hdmi_8996_v3_1p8_vco_clk_ops;
			break;
	default:		default:
	hdmi_vco_clk.c.ops = &hdmi_8996_v1_vco_clk_ops;		hdmi_vco_clk.c.ops = &hdmi_8996_v1_vco_clk_ops;
	break;		break;
	@@ -2414,3 +2476,10 @@ int hdmi_8996_v3_pll_clock_register(struct platform_device *pdev,
	return hdmi_8996_pll_clock_register(pdev, pll_res,		return hdmi_8996_pll_clock_register(pdev, pll_res,
	HDMI_VERSION_8996_V3);		HDMI_VERSION_8996_V3);
	}		}

			int hdmi_8996_v3_1p8_pll_clock_register(struct platform_device *pdev,
			struct mdss_pll_resources *pll_res)
			{
			return hdmi_8996_pll_clock_register(pdev, pll_res,
			HDMI_VERSION_8996_V3_1_8);
			}

drivers/clk/msm/mdss/mdss-hdmi-pll.h

+3 −0

Original line number	Original line	Diff line number	Diff line
	@@ -47,4 +47,7 @@ int hdmi_8996_v2_pll_clock_register(struct platform_device *pdev,

	int hdmi_8996_v3_pll_clock_register(struct platform_device *pdev,		int hdmi_8996_v3_pll_clock_register(struct platform_device *pdev,
	struct mdss_pll_resources *pll_res);		struct mdss_pll_resources *pll_res);

			int hdmi_8996_v3_1p8_pll_clock_register(struct platform_device *pdev,
			struct mdss_pll_resources *pll_res);
	#endif		#endif

drivers/clk/msm/mdss/mdss-pll.c

+7 −0

Original line number	Original line	Diff line number	Diff line
	@@ -146,6 +146,9 @@ static int mdss_pll_resource_parse(struct platform_device *pdev,
	pll_res->pll_interface_type = MDSS_HDMI_PLL_8996_V2;		pll_res->pll_interface_type = MDSS_HDMI_PLL_8996_V2;
	} else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_8996_v3")) {		} else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_8996_v3")) {
	pll_res->pll_interface_type = MDSS_HDMI_PLL_8996_V3;		pll_res->pll_interface_type = MDSS_HDMI_PLL_8996_V3;
			} else if (!strcmp(compatible_stream,
			"qcom,mdss_hdmi_pll_8996_v3_1p8")) {
			pll_res->pll_interface_type = MDSS_HDMI_PLL_8996_V3_1_8;
	} else {		} else {
	goto err;		goto err;
	}		}
	@@ -184,6 +187,9 @@ static int mdss_pll_clock_register(struct platform_device *pdev,
	case MDSS_HDMI_PLL_8996_V3:		case MDSS_HDMI_PLL_8996_V3:
	rc = hdmi_8996_v3_pll_clock_register(pdev, pll_res);		rc = hdmi_8996_v3_pll_clock_register(pdev, pll_res);
	break;		break;
			case MDSS_HDMI_PLL_8996_V3_1_8:
			rc = hdmi_8996_v3_1p8_pll_clock_register(pdev, pll_res);
			break;
	case MDSS_UNKNOWN_PLL:		case MDSS_UNKNOWN_PLL:
	default:		default:
	rc = -EINVAL;		rc = -EINVAL;
	@@ -374,6 +380,7 @@ static const struct of_device_id mdss_pll_dt_match[] = {
	{.compatible = "qcom,mdss_hdmi_pll_8996"},		{.compatible = "qcom,mdss_hdmi_pll_8996"},
	{.compatible = "qcom,mdss_hdmi_pll_8996_v2"},		{.compatible = "qcom,mdss_hdmi_pll_8996_v2"},
	{.compatible = "qcom,mdss_hdmi_pll_8996_v3"},		{.compatible = "qcom,mdss_hdmi_pll_8996_v3"},
			{.compatible = "qcom,mdss_hdmi_pll_8996_v3_1p8"},
	{.compatible = "qcom,mdss_dsi_pll_8952"},		{.compatible = "qcom,mdss_dsi_pll_8952"},
	{.compatible = "qcom,mdss_dsi_pll_8937"},		{.compatible = "qcom,mdss_dsi_pll_8937"},
	{}		{}

drivers/clk/msm/mdss/mdss-pll.h

+1 −0

Original line number	Original line	Diff line number	Diff line
	@@ -33,6 +33,7 @@ enum {
	MDSS_HDMI_PLL_8996,		MDSS_HDMI_PLL_8996,
	MDSS_HDMI_PLL_8996_V2,		MDSS_HDMI_PLL_8996_V2,
	MDSS_HDMI_PLL_8996_V3,		MDSS_HDMI_PLL_8996_V3,
			MDSS_HDMI_PLL_8996_V3_1_8,
	MDSS_UNKNOWN_PLL,		MDSS_UNKNOWN_PLL,
	};		};