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Commit e95d9f95 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-3.14-wip' of git://people.freedesktop.org/~agd5f/linux into drm-next 

This is the drm-next pull for radeon for 3.14. Highlights include:
- dpm rework which fixes some issues and allows us to enable dpm by
default on CIK parts
- enable clockgating on CIK parts
- pci config reset.  This is a bus-level chip reset that can be more
reliable than soft reset in certain cases.  Disabled by default.  Enable
with the hard_reset module option.
- big endian rptr/wrptr update fixes
- lots of debugfs improvements
- some driver cleanup patches from Rashika Kheria
- bug fixes

* 'drm-next-3.14-wip' of git://people.freedesktop.org/~agd5f/linux: (50 commits)
  drm/radeon: implement pci config reset for CIK (v3)
  drm/radeon: implement pci config reset for SI (v2)
  drm/radeon: implement pci config reset for evergreen/cayman (v2)
  drm/radeon: implement pci config reset for r6xx/7xx (v3)
  drm/radeon: add pci config hard reset
  drm/radeon: add hard_reset module parameter
  drm/radeon: skip colorbuffer checking if COLOR_INFO.FORMAT is set to INVALID
  radeon/pm: Guard access to rdev->pm.power_state array
  drivers: gpu: Move prototype declarations to header file radeon_mode.h from radeon_atombios.c and radeon_combios.c
  drivers: gpu: Move prototype declaration to header file radeon_mode.h
  drm/radeon: move com/atombios scratch reg functions to radeon_mode.h
  drm/radeon/dpm: make some functions static for TN
  drm/radeon/dpm: make some functions static for sumo
  drm/radeon/dpm: make some functions static for CI
  drivers: gpu: Include appropriate header file in ci_smc.c
  drivers: gpu: Move prototype declaration to header file radeon_mode.h from atombios_i2c.c
  drivers: gpu: Include appropriate header file in si_smc.c and remove prototype declaration from header file sislands_smc.h
  drivers: gpu: Add static keyword to the definition of KMS_INVALID_IOCTL in radeon_kms.c
  drivers: gpu: Mark function as static in r600_hdmi.c
  drivers: gpu: Mark function as static in radeon_gem.c
  ...
parents feb5cde6 0279ed19

drivers/gpu/drm/radeon/atombios_i2c.c

+0 −2
Original line number Diff line number Diff line
@@ -27,8 +27,6 @@ 
#include "radeon.h"

#include "atom.h"



extern void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);



#define TARGET_HW_I2C_CLOCK 50



/* these are a limitation of ProcessI2cChannelTransaction not the hw */

drivers/gpu/drm/radeon/btc_dpm.c

+5 −15
Original line number Diff line number Diff line
@@ -49,6 +49,7 @@ struct rv7xx_ps *rv770_get_ps(struct radeon_ps *rps); 
struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);

struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);



extern int ni_mc_load_microcode(struct radeon_device *rdev);



//********* BARTS **************//

static const u32 barts_cgcg_cgls_default[] =
@@ -2510,21 +2511,6 @@ int btc_dpm_enable(struct radeon_device *rdev) 
	if (eg_pi->ls_clock_gating)

		btc_ls_clock_gating_enable(rdev, true);



	if (rdev->irq.installed &&

	    r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {

		PPSMC_Result result;



		ret = rv770_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);

		if (ret)

			return ret;

		rdev->irq.dpm_thermal = true;

		radeon_irq_set(rdev);

		result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);



		if (result != PPSMC_Result_OK)

			DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");

	}



	rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);



	btc_init_stutter_mode(rdev);
@@ -2576,7 +2562,11 @@ void btc_dpm_disable(struct radeon_device *rdev) 
void btc_dpm_setup_asic(struct radeon_device *rdev)

{

	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);

	int r;



	r = ni_mc_load_microcode(rdev);

	if (r)

		DRM_ERROR("Failed to load MC firmware!\n");

	rv770_get_memory_type(rdev);

	rv740_read_clock_registers(rdev);

	btc_read_arb_registers(rdev);

drivers/gpu/drm/radeon/ci_dpm.c

+24 −46
Original line number Diff line number Diff line
@@ -171,8 +171,7 @@ extern void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, 
						     struct atom_voltage_table *voltage_table);

extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);

extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);

extern void cik_update_cg(struct radeon_device *rdev,

			  u32 block, bool enable);

extern int ci_mc_load_microcode(struct radeon_device *rdev);



static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,

					 struct atom_voltage_table_entry *voltage_table,
@@ -4503,7 +4502,7 @@ static void ci_get_memory_type(struct radeon_device *rdev) 


}



void ci_update_current_ps(struct radeon_device *rdev,

static void ci_update_current_ps(struct radeon_device *rdev,

				 struct radeon_ps *rps)

{

	struct ci_ps *new_ps = ci_get_ps(rps);
@@ -4514,7 +4513,7 @@ void ci_update_current_ps(struct radeon_device *rdev, 
	pi->current_rps.ps_priv = &pi->current_ps;

}



void ci_update_requested_ps(struct radeon_device *rdev,

static void ci_update_requested_ps(struct radeon_device *rdev,

				   struct radeon_ps *rps)

{

	struct ci_ps *new_ps = ci_get_ps(rps);
@@ -4549,6 +4548,11 @@ void ci_dpm_post_set_power_state(struct radeon_device *rdev) 


void ci_dpm_setup_asic(struct radeon_device *rdev)

{

	int r;



	r = ci_mc_load_microcode(rdev);

	if (r)

		DRM_ERROR("Failed to load MC firmware!\n");

	ci_read_clock_registers(rdev);

	ci_get_memory_type(rdev);

	ci_enable_acpi_power_management(rdev);
@@ -4561,13 +4565,6 @@ int ci_dpm_enable(struct radeon_device *rdev) 
	struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;

	int ret;



	cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |

			     RADEON_CG_BLOCK_MC |

			     RADEON_CG_BLOCK_SDMA |

			     RADEON_CG_BLOCK_BIF |

			     RADEON_CG_BLOCK_UVD |

			     RADEON_CG_BLOCK_HDP), false);



	if (ci_is_smc_running(rdev))

		return -EINVAL;

	if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
@@ -4665,6 +4662,18 @@ int ci_dpm_enable(struct radeon_device *rdev) 
		DRM_ERROR("ci_enable_power_containment failed\n");

		return ret;

	}



	ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);



	ci_update_current_ps(rdev, boot_ps);



	return 0;

}



int ci_dpm_late_enable(struct radeon_device *rdev)

{

	int ret;



	if (rdev->irq.installed &&

	    r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {

#if 0
@@ -4685,19 +4694,8 @@ int ci_dpm_enable(struct radeon_device *rdev) 
#endif

	}



	ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);



	ci_dpm_powergate_uvd(rdev, true);



	cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |

			     RADEON_CG_BLOCK_MC |

			     RADEON_CG_BLOCK_SDMA |

			     RADEON_CG_BLOCK_BIF |

			     RADEON_CG_BLOCK_UVD |

			     RADEON_CG_BLOCK_HDP), true);



	ci_update_current_ps(rdev, boot_ps);



	return 0;

}
@@ -4706,12 +4704,6 @@ void ci_dpm_disable(struct radeon_device *rdev) 
	struct ci_power_info *pi = ci_get_pi(rdev);

	struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;



	cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |

			     RADEON_CG_BLOCK_MC |

			     RADEON_CG_BLOCK_SDMA |

			     RADEON_CG_BLOCK_UVD |

			     RADEON_CG_BLOCK_HDP), false);



	ci_dpm_powergate_uvd(rdev, false);



	if (!ci_is_smc_running(rdev))
@@ -4742,13 +4734,6 @@ int ci_dpm_set_power_state(struct radeon_device *rdev) 
	struct radeon_ps *old_ps = &pi->current_rps;

	int ret;



	cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |

			     RADEON_CG_BLOCK_MC |

			     RADEON_CG_BLOCK_SDMA |

			     RADEON_CG_BLOCK_BIF |

			     RADEON_CG_BLOCK_UVD |

			     RADEON_CG_BLOCK_HDP), false);



	ci_find_dpm_states_clocks_in_dpm_table(rdev, new_ps);

	if (pi->pcie_performance_request)

		ci_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
@@ -4804,13 +4789,6 @@ int ci_dpm_set_power_state(struct radeon_device *rdev) 
	if (pi->pcie_performance_request)

		ci_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);



	cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |

			     RADEON_CG_BLOCK_MC |

			     RADEON_CG_BLOCK_SDMA |

			     RADEON_CG_BLOCK_BIF |

			     RADEON_CG_BLOCK_UVD |

			     RADEON_CG_BLOCK_HDP), true);



	return 0;

}
@@ -5023,7 +5001,7 @@ static int ci_parse_power_table(struct radeon_device *rdev) 
	return 0;

}



int ci_get_vbios_boot_values(struct radeon_device *rdev,

static int ci_get_vbios_boot_values(struct radeon_device *rdev,

				    struct ci_vbios_boot_state *boot_state)

{

	struct radeon_mode_info *mode_info = &rdev->mode_info;

drivers/gpu/drm/radeon/ci_smc.c

+1 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ 
#include "cikd.h"

#include "ppsmc.h"

#include "radeon_ucode.h"

#include "ci_dpm.h"



static int ci_set_smc_sram_address(struct radeon_device *rdev,

				   u32 smc_address, u32 limit)

drivers/gpu/drm/radeon/cik.c

+230 −38
Original line number Diff line number Diff line
@@ -1697,7 +1697,7 @@ static void cik_srbm_select(struct radeon_device *rdev, 
 * Load the GDDR MC ucode into the hw (CIK).

 * Returns 0 on success, error on failure.

 */

static int ci_mc_load_microcode(struct radeon_device *rdev)

int ci_mc_load_microcode(struct radeon_device *rdev)

{

	const __be32 *fw_data;

	u32 running, blackout = 0;
@@ -4015,15 +4015,43 @@ static int cik_cp_gfx_resume(struct radeon_device *rdev) 
	return 0;

}



u32 cik_compute_ring_get_rptr(struct radeon_device *rdev,

u32 cik_gfx_get_rptr(struct radeon_device *rdev,

		     struct radeon_ring *ring)

{

	u32 rptr;



	if (rdev->wb.enabled)

		rptr = rdev->wb.wb[ring->rptr_offs/4];

	else

		rptr = RREG32(CP_RB0_RPTR);



	return rptr;

}



u32 cik_gfx_get_wptr(struct radeon_device *rdev,

		     struct radeon_ring *ring)

{

	u32 wptr;



	wptr = RREG32(CP_RB0_WPTR);



	return wptr;

}



void cik_gfx_set_wptr(struct radeon_device *rdev,

		      struct radeon_ring *ring)

{

	WREG32(CP_RB0_WPTR, ring->wptr);

	(void)RREG32(CP_RB0_WPTR);

}



u32 cik_compute_get_rptr(struct radeon_device *rdev,

			 struct radeon_ring *ring)

{

	u32 rptr;



	if (rdev->wb.enabled) {

		rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);

		rptr = rdev->wb.wb[ring->rptr_offs/4];

	} else {

		mutex_lock(&rdev->srbm_mutex);

		cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);
@@ -4035,13 +4063,14 @@ u32 cik_compute_ring_get_rptr(struct radeon_device *rdev, 
	return rptr;

}



u32 cik_compute_ring_get_wptr(struct radeon_device *rdev,

u32 cik_compute_get_wptr(struct radeon_device *rdev,

			 struct radeon_ring *ring)

{

	u32 wptr;



	if (rdev->wb.enabled) {

		wptr = le32_to_cpu(rdev->wb.wb[ring->wptr_offs/4]);

		/* XXX check if swapping is necessary on BE */

		wptr = rdev->wb.wb[ring->wptr_offs/4];

	} else {

		mutex_lock(&rdev->srbm_mutex);

		cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);
@@ -4053,10 +4082,11 @@ u32 cik_compute_ring_get_wptr(struct radeon_device *rdev, 
	return wptr;

}



void cik_compute_ring_set_wptr(struct radeon_device *rdev,

void cik_compute_set_wptr(struct radeon_device *rdev,

			  struct radeon_ring *ring)

{

	rdev->wb.wb[ring->wptr_offs/4] = cpu_to_le32(ring->wptr);

	/* XXX check if swapping is necessary on BE */

	rdev->wb.wb[ring->wptr_offs/4] = ring->wptr;

	WDOORBELL32(ring->doorbell_index, ring->wptr);

}
@@ -4850,6 +4880,160 @@ static void cik_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) 
	cik_print_gpu_status_regs(rdev);

}



struct kv_reset_save_regs {

	u32 gmcon_reng_execute;

	u32 gmcon_misc;

	u32 gmcon_misc3;

};



static void kv_save_regs_for_reset(struct radeon_device *rdev,

				   struct kv_reset_save_regs *save)

{

	save->gmcon_reng_execute = RREG32(GMCON_RENG_EXECUTE);

	save->gmcon_misc = RREG32(GMCON_MISC);

	save->gmcon_misc3 = RREG32(GMCON_MISC3);



	WREG32(GMCON_RENG_EXECUTE, save->gmcon_reng_execute & ~RENG_EXECUTE_ON_PWR_UP);

	WREG32(GMCON_MISC, save->gmcon_misc & ~(RENG_EXECUTE_ON_REG_UPDATE |

						STCTRL_STUTTER_EN));

}



static void kv_restore_regs_for_reset(struct radeon_device *rdev,

				      struct kv_reset_save_regs *save)

{

	int i;



	WREG32(GMCON_PGFSM_WRITE, 0);

	WREG32(GMCON_PGFSM_CONFIG, 0x200010ff);



	for (i = 0; i < 5; i++)

		WREG32(GMCON_PGFSM_WRITE, 0);



	WREG32(GMCON_PGFSM_WRITE, 0);

	WREG32(GMCON_PGFSM_CONFIG, 0x300010ff);



	for (i = 0; i < 5; i++)

		WREG32(GMCON_PGFSM_WRITE, 0);



	WREG32(GMCON_PGFSM_WRITE, 0x210000);

	WREG32(GMCON_PGFSM_CONFIG, 0xa00010ff);



	for (i = 0; i < 5; i++)

		WREG32(GMCON_PGFSM_WRITE, 0);



	WREG32(GMCON_PGFSM_WRITE, 0x21003);

	WREG32(GMCON_PGFSM_CONFIG, 0xb00010ff);



	for (i = 0; i < 5; i++)

		WREG32(GMCON_PGFSM_WRITE, 0);



	WREG32(GMCON_PGFSM_WRITE, 0x2b00);

	WREG32(GMCON_PGFSM_CONFIG, 0xc00010ff);



	for (i = 0; i < 5; i++)

		WREG32(GMCON_PGFSM_WRITE, 0);



	WREG32(GMCON_PGFSM_WRITE, 0);

	WREG32(GMCON_PGFSM_CONFIG, 0xd00010ff);



	for (i = 0; i < 5; i++)

		WREG32(GMCON_PGFSM_WRITE, 0);



	WREG32(GMCON_PGFSM_WRITE, 0x420000);

	WREG32(GMCON_PGFSM_CONFIG, 0x100010ff);



	for (i = 0; i < 5; i++)

		WREG32(GMCON_PGFSM_WRITE, 0);



	WREG32(GMCON_PGFSM_WRITE, 0x120202);

	WREG32(GMCON_PGFSM_CONFIG, 0x500010ff);



	for (i = 0; i < 5; i++)

		WREG32(GMCON_PGFSM_WRITE, 0);



	WREG32(GMCON_PGFSM_WRITE, 0x3e3e36);

	WREG32(GMCON_PGFSM_CONFIG, 0x600010ff);



	for (i = 0; i < 5; i++)

		WREG32(GMCON_PGFSM_WRITE, 0);



	WREG32(GMCON_PGFSM_WRITE, 0x373f3e);

	WREG32(GMCON_PGFSM_CONFIG, 0x700010ff);



	for (i = 0; i < 5; i++)

		WREG32(GMCON_PGFSM_WRITE, 0);



	WREG32(GMCON_PGFSM_WRITE, 0x3e1332);

	WREG32(GMCON_PGFSM_CONFIG, 0xe00010ff);



	WREG32(GMCON_MISC3, save->gmcon_misc3);

	WREG32(GMCON_MISC, save->gmcon_misc);

	WREG32(GMCON_RENG_EXECUTE, save->gmcon_reng_execute);

}



static void cik_gpu_pci_config_reset(struct radeon_device *rdev)

{

	struct evergreen_mc_save save;

	struct kv_reset_save_regs kv_save = { 0 };

	u32 tmp, i;



	dev_info(rdev->dev, "GPU pci config reset\n");



	/* disable dpm? */



	/* disable cg/pg */

	cik_fini_pg(rdev);

	cik_fini_cg(rdev);



	/* Disable GFX parsing/prefetching */

	WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);



	/* Disable MEC parsing/prefetching */

	WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT);



	/* sdma0 */

	tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);

	tmp |= SDMA_HALT;

	WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);

	/* sdma1 */

	tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);

	tmp |= SDMA_HALT;

	WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp);

	/* XXX other engines? */



	/* halt the rlc, disable cp internal ints */

	cik_rlc_stop(rdev);



	udelay(50);



	/* disable mem access */

	evergreen_mc_stop(rdev, &save);

	if (evergreen_mc_wait_for_idle(rdev)) {

		dev_warn(rdev->dev, "Wait for MC idle timed out !\n");

	}



	if (rdev->flags & RADEON_IS_IGP)

		kv_save_regs_for_reset(rdev, &kv_save);



	/* disable BM */

	pci_clear_master(rdev->pdev);

	/* reset */

	radeon_pci_config_reset(rdev);



	udelay(100);



	/* wait for asic to come out of reset */

	for (i = 0; i < rdev->usec_timeout; i++) {

		if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)

			break;

		udelay(1);

	}



	/* does asic init need to be run first??? */

	if (rdev->flags & RADEON_IS_IGP)

		kv_restore_regs_for_reset(rdev, &kv_save);

}



/**

 * cik_asic_reset - soft reset GPU

 *
@@ -4868,10 +5052,17 @@ int cik_asic_reset(struct radeon_device *rdev) 
	if (reset_mask)

		r600_set_bios_scratch_engine_hung(rdev, true);



	/* try soft reset */

	cik_gpu_soft_reset(rdev, reset_mask);



	reset_mask = cik_gpu_check_soft_reset(rdev);



	/* try pci config reset */

	if (reset_mask && radeon_hard_reset)

		cik_gpu_pci_config_reset(rdev);



	reset_mask = cik_gpu_check_soft_reset(rdev);



	if (!reset_mask)

		r600_set_bios_scratch_engine_hung(rdev, false);
@@ -7501,26 +7692,7 @@ static int cik_startup(struct radeon_device *rdev) 


	cik_mc_program(rdev);



	if (rdev->flags & RADEON_IS_IGP) {

		if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||

		    !rdev->mec_fw || !rdev->sdma_fw || !rdev->rlc_fw) {

			r = cik_init_microcode(rdev);

			if (r) {

				DRM_ERROR("Failed to load firmware!\n");

				return r;

			}

		}

	} else {

		if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||

		    !rdev->mec_fw || !rdev->sdma_fw || !rdev->rlc_fw ||

		    !rdev->mc_fw) {

			r = cik_init_microcode(rdev);

			if (r) {

				DRM_ERROR("Failed to load firmware!\n");

				return r;

			}

		}



	if (!(rdev->flags & RADEON_IS_IGP) && !rdev->pm.dpm_enabled) {

		r = ci_mc_load_microcode(rdev);

		if (r) {

			DRM_ERROR("Failed to load MC firmware!\n");
@@ -7625,7 +7797,6 @@ static int cik_startup(struct radeon_device *rdev) 


	ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];

	r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,

			     CP_RB0_RPTR, CP_RB0_WPTR,

			     PACKET3(PACKET3_NOP, 0x3FFF));

	if (r)

		return r;
@@ -7634,7 +7805,6 @@ static int cik_startup(struct radeon_device *rdev) 
	/* type-2 packets are deprecated on MEC, use type-3 instead */

	ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];

	r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,

			     CP_HQD_PQ_RPTR, CP_HQD_PQ_WPTR,

			     PACKET3(PACKET3_NOP, 0x3FFF));

	if (r)

		return r;
@@ -7646,7 +7816,6 @@ static int cik_startup(struct radeon_device *rdev) 
	/* type-2 packets are deprecated on MEC, use type-3 instead */

	ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];

	r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,

			     CP_HQD_PQ_RPTR, CP_HQD_PQ_WPTR,

			     PACKET3(PACKET3_NOP, 0x3FFF));

	if (r)

		return r;
@@ -7658,16 +7827,12 @@ static int cik_startup(struct radeon_device *rdev) 


	ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];

	r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,

			     SDMA0_GFX_RB_RPTR + SDMA0_REGISTER_OFFSET,

			     SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET,

			     SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));

	if (r)

		return r;



	ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];

	r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,

			     SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET,

			     SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET,

			     SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));

	if (r)

		return r;
@@ -7683,7 +7848,6 @@ static int cik_startup(struct radeon_device *rdev) 
	ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];

	if (ring->ring_size) {

		r = radeon_ring_init(rdev, ring, ring->ring_size, 0,

				     UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,

				     RADEON_CP_PACKET2);

		if (!r)

			r = uvd_v1_0_init(rdev);
@@ -7729,6 +7893,8 @@ int cik_resume(struct radeon_device *rdev) 
	/* init golden registers */

	cik_init_golden_registers(rdev);



	radeon_pm_resume(rdev);



	rdev->accel_working = true;

	r = cik_startup(rdev);

	if (r) {
@@ -7752,6 +7918,7 @@ int cik_resume(struct radeon_device *rdev) 
 */

int cik_suspend(struct radeon_device *rdev)

{

	radeon_pm_suspend(rdev);

	dce6_audio_fini(rdev);

	radeon_vm_manager_fini(rdev);

	cik_cp_enable(rdev, false);
@@ -7833,6 +8000,30 @@ int cik_init(struct radeon_device *rdev) 
	if (r)

		return r;



	if (rdev->flags & RADEON_IS_IGP) {

		if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||

		    !rdev->mec_fw || !rdev->sdma_fw || !rdev->rlc_fw) {

			r = cik_init_microcode(rdev);

			if (r) {

				DRM_ERROR("Failed to load firmware!\n");

				return r;

			}

		}

	} else {

		if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||

		    !rdev->mec_fw || !rdev->sdma_fw || !rdev->rlc_fw ||

		    !rdev->mc_fw) {

			r = cik_init_microcode(rdev);

			if (r) {

				DRM_ERROR("Failed to load firmware!\n");

				return r;

			}

		}

	}



	/* Initialize power management */

	radeon_pm_init(rdev);



	ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];

	ring->ring_obj = NULL;

	r600_ring_init(rdev, ring, 1024 * 1024);
@@ -7913,6 +8104,7 @@ int cik_init(struct radeon_device *rdev) 
 */

void cik_fini(struct radeon_device *rdev)

{

	radeon_pm_fini(rdev);

	cik_cp_fini(rdev);

	cik_sdma_fini(rdev);

	cik_fini_pg(rdev);