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Commit e951cbf2 authored by Guennadi Liakhovetski's avatar Guennadi Liakhovetski Committed by Mauro Carvalho Chehab
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V4L/DVB (11326): mt9m001: fix advertised pixel clock polarity 



MT9M001 datasheet says, that the data is ready on the falling edge of the pixel
clock, but the driver wrongly sets the SOCAM_PCLK_SAMPLE_RISING flag. Changing
this doesn't seem to produce any visible difference, still, it is better to
comply to the datasheet.

Reported-by: default avatarSascha Oppermann <oppermann@garage-computers.com>
Signed-off-by: default avatarGuennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@redhat.com>
parent eee1663f

drivers/media/video/mt9m001.c

+1 −1
Original line number Diff line number Diff line
@@ -207,7 +207,7 @@ static unsigned long mt9m001_query_bus_param(struct soc_camera_device *icd) 
	struct mt9m001 *mt9m001 = container_of(icd, struct mt9m001, icd);

	struct soc_camera_link *icl = mt9m001->client->dev.platform_data;

	/* MT9M001 has all capture_format parameters fixed */

	unsigned long flags = SOCAM_PCLK_SAMPLE_RISING |

	unsigned long flags = SOCAM_PCLK_SAMPLE_FALLING |

		SOCAM_HSYNC_ACTIVE_HIGH | SOCAM_VSYNC_ACTIVE_HIGH |

		SOCAM_DATA_ACTIVE_HIGH | SOCAM_MASTER;