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Commit e948e994 authored by Keith Packard's avatar Keith Packard Committed by Dave Airlie
Browse files

drm/i915: save and restore dsparb and d_state registers. 



Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent a59e122a

drivers/char/drm/i915_drv.c

+7 −0
Original line number Diff line number Diff line
@@ -256,6 +256,9 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state) 
	pci_save_state(dev->pdev);

	pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);



	/* Display arbitration control */

	dev_priv->saveDSPARB = I915_READ(DSPARB);



	/* Pipe & plane A info */

	dev_priv->savePIPEACONF = I915_READ(PIPEACONF);

	dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
@@ -349,6 +352,7 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state) 
	dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);



	/* Clock gating state */

	dev_priv->saveD_STATE = I915_READ(D_STATE);

	dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D);



	/* Cache mode state */
@@ -388,6 +392,8 @@ static int i915_resume(struct drm_device *dev) 


	pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);



	I915_WRITE(DSPARB, dev_priv->saveDSPARB);



	/* Pipe & plane A info */

	/* Prime the clock */

	if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
@@ -507,6 +513,7 @@ static int i915_resume(struct drm_device *dev) 
	udelay(150);



	/* Clock gating state */

	I915_WRITE (D_STATE, dev_priv->saveD_STATE);

	I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D);



	/* Cache mode state */

drivers/char/drm/i915_drv.h

+10 −0
Original line number Diff line number Diff line
@@ -119,6 +119,7 @@ typedef struct drm_i915_private { 
	u8 saveLBB;

	u32 saveDSPACNTR;

	u32 saveDSPBCNTR;

	u32 saveDSPARB;

	u32 savePIPEACONF;

	u32 savePIPEBCONF;

	u32 savePIPEASRC;
@@ -188,6 +189,7 @@ typedef struct drm_i915_private { 
	u32 saveIIR;

	u32 saveIMR;

	u32 saveCACHE_MODE_0;

	u32 saveD_STATE;

	u32 saveDSPCLK_GATE_D;

	u32 saveMI_ARB_STATE;

	u32 saveSWF0[16];
@@ -670,6 +672,8 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); 
/** P1 value is 2 greater than this field */

# define VGA0_PD_P1_MASK	(0x1f << 0)



/* PCI D state control register */

#define D_STATE		0x6104

#define DSPCLK_GATE_D	0x6200



/* I830 CRTC registers */
@@ -980,6 +984,12 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); 
#define PIPECONF_INTERLACE_W_FIELD_INDICATION	(6 << 21)

#define PIPECONF_INTERLACE_FIELD_0_ONLY		(7 << 21)



#define DSPARB	  0x70030

#define DSPARB_CSTART_MASK	(0x7f << 7)

#define DSPARB_CSTART_SHIFT	7

#define DSPARB_BSTART_MASK	(0x7f)		 

#define DSPARB_BSTART_SHIFT	0



#define PIPEBCONF 0x71008

#define PIPEBCONF_ENABLE	(1<<31)

#define PIPEBCONF_DISABLE	0