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Commit e898c791 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2014-07-18' of git://anongit.freedesktop.org/drm-intel 

But in any case nothing really shocking in
here, 2 reverts, 1 quirk and a regression fix a WARN.

* tag 'drm-intel-fixes-2014-07-18' of git://anongit.freedesktop.org/drm-intel:
  Revert "drm/i915: reverse dp link param selection, prefer fast over wide again"
  drm/i915: Track the primary plane correctly when reassigning planes
  drm/i915: Ignore VBT backlight presence check on HP Chromebook 14
  Revert "drm/i915: Don't set the 8to6 dither flag when not scaling"
parents b579fcca c6930992

drivers/gpu/drm/i915/intel_display.c

+4 −0
Original line number Diff line number Diff line
@@ -11673,6 +11673,9 @@ static struct intel_quirk intel_quirks[] = { 


	/* Toshiba CB35 Chromebook (Celeron 2955U) */

	{ 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },



	/* HP Chromebook 14 (Celeron 2955U) */

	{ 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },

};



static void intel_init_quirks(struct drm_device *dev)
@@ -11911,6 +11914,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc) 
		 * ...  */

		plane = crtc->plane;

		crtc->plane = !plane;

		crtc->primary_enabled = true;

		dev_priv->display.crtc_disable(&crtc->base);

		crtc->plane = plane;

drivers/gpu/drm/i915/intel_dp.c

+2 −2
Original line number Diff line number Diff line
@@ -906,8 +906,8 @@ intel_dp_compute_config(struct intel_encoder *encoder, 
		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,

						   bpp);



		for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {

		for (clock = min_clock; clock <= max_clock; clock++) {

			for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {

				link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);

				link_avail = intel_dp_max_data_rate(link_clock,

								    lane_count);

drivers/gpu/drm/i915/intel_lvds.c

+7 −0
Original line number Diff line number Diff line
@@ -111,6 +111,13 @@ static void intel_lvds_get_config(struct intel_encoder *encoder, 


	pipe_config->adjusted_mode.flags |= flags;



	/* gen2/3 store dither state in pfit control, needs to match */

	if (INTEL_INFO(dev)->gen < 4) {

		tmp = I915_READ(PFIT_CONTROL);



		pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;

	}



	dotclock = pipe_config->port_clock;



	if (HAS_PCH_SPLIT(dev_priv->dev))

drivers/gpu/drm/i915/intel_panel.c

+4 −4
Original line number Diff line number Diff line
@@ -361,16 +361,16 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc, 
		pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |

				 PFIT_FILTER_FUZZY);



	/* Make sure pre-965 set dither correctly for 18bpp panels. */

	if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18)

		pfit_control |= PANEL_8TO6_DITHER_ENABLE;



out:

	if ((pfit_control & PFIT_ENABLE) == 0) {

		pfit_control = 0;

		pfit_pgm_ratios = 0;

	}



	/* Make sure pre-965 set dither correctly for 18bpp panels. */

	if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18)

		pfit_control |= PANEL_8TO6_DITHER_ENABLE;



	pipe_config->gmch_pfit.control = pfit_control;

	pipe_config->gmch_pfit.pgm_ratios = pfit_pgm_ratios;

	pipe_config->gmch_pfit.lvds_border_bits = border;