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Commit e7b8b7f1 authored by Paul Mundt's avatar Paul Mundt
Browse files

sh: NO_CONTEXT ASID optimizations for SH-4 cache flush. 



This optimizes for the cases when a CPU does not yet have a valid ASID
context associated with it, as in this case there is no work for any of
flush_cache_mm()/flush_cache_page()/flush_cache_range() to do. Based on
the the MIPS implementation.

Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent 79568726

arch/sh/mm/cache-sh4.c

+9 −0
Original line number Diff line number Diff line
@@ -330,6 +330,9 @@ loop_exit: 
 */

void flush_cache_mm(struct mm_struct *mm)

{

	if (cpu_context(smp_processor_id(), mm) == NO_CONTEXT)

		return;



	/*

	 * If cache is only 4k-per-way, there are never any 'aliases'.  Since

	 * the cache is physically tagged, the data can just be left in there.
@@ -371,6 +374,9 @@ void flush_cache_page(struct vm_area_struct *vma, unsigned long address, 
	unsigned long phys = pfn << PAGE_SHIFT;

	unsigned int alias_mask;



	if (cpu_context(smp_processor_id(), vma->vm_mm) == NO_CONTEXT)

		return;



	alias_mask = boot_cpu_data.dcache.alias_mask;



	/* We only need to flush D-cache when we have alias */
@@ -413,6 +419,9 @@ void flush_cache_page(struct vm_area_struct *vma, unsigned long address, 
void flush_cache_range(struct vm_area_struct *vma, unsigned long start,

		       unsigned long end)

{

	if (cpu_context(smp_processor_id(), vma->vm_mm) == NO_CONTEXT)

		return;



	/*

	 * If cache is only 4k-per-way, there are never any 'aliases'.  Since

	 * the cache is physically tagged, the data can just be left in there.