CRIS: v32: Better irq mapping code (e75a320e) · Commits · e / devices / android_kernel_xiaomi_markw

arch/cris/arch-v32/kernel/irq.c

+22 −25

Original line number	Original line	Diff line number	Diff line
	@@ -97,7 +97,11 @@ extern void breakh_BUG(void);
	/*		/*
	* Build the IRQ handler stubs using macros from irq.h.		* Build the IRQ handler stubs using macros from irq.h.
	*/		*/
			#ifdef CONFIG_CRIS_MACH_ARTPEC3
			BUILD_TIMER_IRQ(0x31, 0)
			#else
	BUILD_IRQ(0x31)		BUILD_IRQ(0x31)
			#endif
	BUILD_IRQ(0x32)		BUILD_IRQ(0x32)
	BUILD_IRQ(0x33)		BUILD_IRQ(0x33)
	BUILD_IRQ(0x34)		BUILD_IRQ(0x34)
	@@ -123,7 +127,11 @@ BUILD_IRQ(0x47)
	BUILD_IRQ(0x48)		BUILD_IRQ(0x48)
	BUILD_IRQ(0x49)		BUILD_IRQ(0x49)
	BUILD_IRQ(0x4a)		BUILD_IRQ(0x4a)
			#ifdef CONFIG_ETRAXFS
			BUILD_TIMER_IRQ(0x4b, 0)
			#else
	BUILD_IRQ(0x4b)		BUILD_IRQ(0x4b)
			#endif
	BUILD_IRQ(0x4c)		BUILD_IRQ(0x4c)
	BUILD_IRQ(0x4d)		BUILD_IRQ(0x4d)
	BUILD_IRQ(0x4e)		BUILD_IRQ(0x4e)
	@@ -199,25 +207,20 @@ block_irq(int irq, int cpu)
	unsigned long flags;		unsigned long flags;

	spin_lock_irqsave(&irq_lock, flags);		spin_lock_irqsave(&irq_lock, flags);
	if (irq - FIRST_IRQ < 32)		/* Remember, 1 let thru, 0 block. */
			if (irq - FIRST_IRQ < 32) {
	intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],		intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
	rw_mask, 0);		rw_mask, 0);
	else
	intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
	rw_mask, 1);

	/* Remember; 1 let thru, 0 block. */
	if (irq - FIRST_IRQ < 32)
	intr_mask &= ~(1 << (irq - FIRST_IRQ));		intr_mask &= ~(1 << (irq - FIRST_IRQ));
	else
	intr_mask &= ~(1 << (irq - FIRST_IRQ - 32));

	if (irq - FIRST_IRQ < 32)
	REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,		REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
	0, intr_mask);		0, intr_mask);
	else		} else {
			intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
			rw_mask, 1);
			intr_mask &= ~(1 << (irq - FIRST_IRQ - 32));
	REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,		REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
	1, intr_mask);		1, intr_mask);
			}
	spin_unlock_irqrestore(&irq_lock, flags);		spin_unlock_irqrestore(&irq_lock, flags);
	}		}

	@@ -228,26 +231,20 @@ unblock_irq(int irq, int cpu)
	unsigned long flags;		unsigned long flags;

	spin_lock_irqsave(&irq_lock, flags);		spin_lock_irqsave(&irq_lock, flags);
	if (irq - FIRST_IRQ < 32)		/* Remember, 1 let thru, 0 block. */
			if (irq - FIRST_IRQ < 32) {
	intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],		intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
	rw_mask, 0);		rw_mask, 0);
	else
	intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
	rw_mask, 1);

	/* Remember; 1 let thru, 0 block. */
	if (irq - FIRST_IRQ < 32)
	intr_mask \|= (1 << (irq - FIRST_IRQ));		intr_mask \|= (1 << (irq - FIRST_IRQ));
	else
	intr_mask \|= (1 << (irq - FIRST_IRQ - 32));

	if (irq - FIRST_IRQ < 32)
	REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,		REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
	0, intr_mask);		0, intr_mask);
	else		} else {
			intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
			rw_mask, 1);
			intr_mask \|= (1 << (irq - FIRST_IRQ - 32));
	REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,		REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
	1, intr_mask);		1, intr_mask);
			}
	spin_unlock_irqrestore(&irq_lock, flags);		spin_unlock_irqrestore(&irq_lock, flags);
	}		}