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Commit e703fd87 authored by Stepan Moskovchenko's avatar Stepan Moskovchenko Committed by Matt Wagantall
Browse files

arm64: Add options to disable I/D caches 



Add the ability to individually disable the Instruction and
Data caches on ARM64 CPUs, by means of the SCTLR[I] and
SCTLR[C] bits. This may be useful for performance
profiling, as well as for troubleshooting potential cache
problems.

Change-Id: Ibd7fc796ddf6984c7f05dcd844432164e28bb021
Signed-off-by: default avatarStepan Moskovchenko <stepanm@codeaurora.org>
[abhimany: resolve trivial merge conflicts]
Signed-off-by: default avatarAbhimanyu Kapur <abhimany@codeaurora.org>
parent df251bff

arch/arm64/Kconfig

+19 −0
Original line number Diff line number Diff line
@@ -224,6 +224,25 @@ config ARM64_4K_PAGES 
	help

	  This feature enables 4KB pages support.



config ARM64_DCACHE_DISABLE

	bool "Disable CPU Data Caches"

	help

	  Disable CPU data cache usage by setting the SCTLR[C] bit during

	  kernel initialization. This will result in a considerable

	  performance impact, but may be useful in certain situations.



	  If you are not sure what to do, select 'N' here.



config ARM64_ICACHE_DISABLE

	bool "Disable CPU Instruction Caches"

	help

	  Disable CPU instruction cache usage by setting the SCTLR[I]

	  bit during kernel initialization. This will result in a

	  considerable performance impact, but may be useful in certain

	  situations.



	  If you are not sure what to do, select 'N' here.



config ARM64_64K_PAGES

	bool "64KB"

	help

arch/arm64/mm/proc.S

+15 −2
Original line number Diff line number Diff line
@@ -253,5 +253,18 @@ ENDPROC(__cpu_setup) 
	 */

	.type	crval, #object

crval:



#ifdef CONFIG_ARM64_ICACHE_DISABLE

#define CR_IBIT		0

#else

#define CR_IBIT		0x1000

#endif



#ifdef CONFIG_ARM64_DCACHE_DISABLE

#define CR_CBIT		0

#else

#define CR_CBIT		0x4

#endif



	.word	0x000802c2	// clear

	.word	0x0405d13d			// set
 
	.word	0x0405c139 | CR_IBIT | CR_CBIT	// set