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Commit e6ee80ad authored by Oleg Perelet's avatar Oleg Perelet
Browse files

msm: kgsl: Pass GPU leakage value to limits management 



Read value for GPU leakage from e-fuse and pass it to GPMU.

Change-Id: Ibe61db99a7a474effe0a12f40c7e399c454b76ab
Signed-off-by: default avatarOleg Perelet <operelet@codeaurora.org>
parent 162e9ed4

Documentation/devicetree/bindings/gpu/adreno.txt

+3 −0
Original line number Diff line number Diff line
@@ -33,6 +33,9 @@ Required properties: 
				"alt_mem_iface_clk", "rbbmtimer_clk"

				"core_clk" and "iface_clk" are required and others are optional



- qcom,gpu-efuse-leakage:	memory region for GPU power rail leakage.

- qcom,base-leakage-coefficient: Dynamic leakage coefficient.



Bus Scaling Data:

- qcom,msm-bus,name: String property to describe the name of the 3D graphics processor.

- qcom,msm-bus,num-cases: This is the the number of Bus Scaling use cases defined in the vectors property.

arch/arm/boot/dts/qcom/msm8996-gpu.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -56,6 +56,8 @@ 
		qcom,id = <0>;



		qcom,chipid = <0x05030000>;

		qcom,gpu-efuse-leakage = <0x00070130 24>;

		qcom,base-leakage-coefficient = <34>;



		qcom,initial-pwrlevel = <2>;

drivers/gpu/msm/adreno.h

+1 −0
Original line number Diff line number Diff line
@@ -342,6 +342,7 @@ struct adreno_device { 
	uint32_t lm_size;

	struct kgsl_memdesc preemption_counters;

	struct work_struct gpmu_work;

	uint32_t lm_leakage;

};



/**

drivers/gpu/msm/adreno_a5xx.c

+42 −2
Original line number Diff line number Diff line
@@ -99,6 +99,8 @@ static void a5xx_gpmu_reset(struct work_struct *work); 


#define AGC_POWER_CONFIG_PRODUCTION_ID	1



#define GFX_DEFAULT_LEAKAGE 0x004E001A



/*

 * a5xx_preemption_start() - Setup state to start preemption

 */
@@ -1297,6 +1299,42 @@ static void _write_voltage_table(struct adreno_device *adreno_dev, 
	*length = levels * 2 + 2;

}



static uint32_t gfx_base_leakage(struct adreno_device *adreno_dev)

{

	struct kgsl_device *device = &adreno_dev->dev;

	void __iomem *base;

	uint32_t gfx_active, multiplier, leakage_pwr_on, coeff, leakagemem[2];



	if (adreno_dev->lm_leakage)

		return adreno_dev->lm_leakage;



	adreno_dev->lm_leakage = GFX_DEFAULT_LEAKAGE;



	if (of_property_read_u32_array(device->pdev->dev.of_node,

		"qcom,gpu-efuse-leakage", leakagemem, 2))

		return adreno_dev->lm_leakage;



	if (!leakagemem[0] || !leakagemem[1])

		return adreno_dev->lm_leakage;



	base = ioremap(leakagemem[0], leakagemem[1]);

	if (!base)

		return adreno_dev->lm_leakage;



	multiplier = (uint32_t) ((readq(base) >> 33) & 0x3);

	gfx_active = (uint32_t) ((readq(base + 16) >> 34) & 0xff);

	iounmap(base);



	if (of_property_read_u32(device->pdev->dev.of_node,

		"qcom,base-leakage-coefficient", &coeff) || !coeff)

		return adreno_dev->lm_leakage;



	leakage_pwr_on = gfx_active * (1 << multiplier);

	adreno_dev->lm_leakage = (leakage_pwr_on << 16) |

		(leakage_pwr_on * coeff) / 100;

	return adreno_dev->lm_leakage;

}



/*

 * a5xx_lm_init() - Initialize LM/DPM on the GPMU

 * @adreno_dev: The adreno device pointer
@@ -1331,8 +1369,10 @@ static void a5xx_lm_init(struct adreno_device *adreno_dev) 


	kgsl_regwrite(device, A5XX_GPMU_GPMU_VOLTAGE,

			(0x80000000 | device->pwrctrl.active_pwrlevel));

	/* todo use the iddq fuse to correct this value at runtime */

	kgsl_regwrite(device, A5XX_GPMU_BASE_LEAKAGE, 0x00640002);

	/* use the leakage to set this value at runtime */

	kgsl_regwrite(device, A5XX_GPMU_BASE_LEAKAGE,

		gfx_base_leakage(adreno_dev));



	/* default of 6A */

	kgsl_regwrite(device, A5XX_GPMU_GPMU_PWR_THRESHOLD, 0x80001000);