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Commit e5abf78b authored by GuanXuetao's avatar GuanXuetao
Browse files

unicore32 io: redefine __REG(x) and re-use readl/writel funcs 



  -- by advice of Arnd Bergmann

Signed-off-by: default avatarGuan Xuetao <gxt@mprc.pku.edu.cn>
Reviewed-by: default avatarArnd Bergmann <arnd@arndb.de>
parent 4517366d

arch/unicore32/include/asm/gpio.h

+5 −4
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 
#ifndef __UNICORE_GPIO_H__

#define __UNICORE_GPIO_H__



#include <linux/io.h>

#include <asm/irq.h>

#include <mach/hardware.h>

#include <asm-generic/gpio.h>
@@ -66,7 +67,7 @@ 
static inline int gpio_get_value(unsigned gpio)

{

	if (__builtin_constant_p(gpio) && (gpio <= GPIO_MAX))

		return GPIO_GPLR & GPIO_GPIO(gpio);

		return readl(GPIO_GPLR) & GPIO_GPIO(gpio);

	else

		return __gpio_get_value(gpio);

}
@@ -75,9 +76,9 @@ static inline void gpio_set_value(unsigned gpio, int value) 
{

	if (__builtin_constant_p(gpio) && (gpio <= GPIO_MAX))

		if (value)

			GPIO_GPSR = GPIO_GPIO(gpio);

			writel(GPIO_GPIO(gpio), GPIO_GPSR);

		else

			GPIO_GPCR = GPIO_GPIO(gpio);

			writel(GPIO_GPIO(gpio), GPIO_GPCR);

	else

		__gpio_set_value(gpio, value);

}
@@ -86,7 +87,7 @@ static inline void gpio_set_value(unsigned gpio, int value) 


static inline unsigned gpio_to_irq(unsigned gpio)

{

	if ((gpio < IRQ_GPIOHIGH) && (FIELD(1, 1, gpio) & GPIO_GPIR))

	if ((gpio < IRQ_GPIOHIGH) && (FIELD(1, 1, gpio) & readl(GPIO_GPIR)))

		return IRQ_GPIOLOW0 + gpio;

	else

		return IRQ_GPIO0 + gpio;

arch/unicore32/include/mach/dma.h

+9 −2
Original line number Diff line number Diff line
@@ -35,7 +35,14 @@ extern int puv3_request_dma(char *name, 


extern void puv3_free_dma(int dma_ch);



#define puv3_stop_dma(ch)		(DMAC_CONFIG(ch) &= ~DMAC_CONFIG_EN)

#define puv3_resume_dma(ch)             (DMAC_CONFIG(ch) |= DMAC_CONFIG_EN)

static inline void puv3_stop_dma(int ch)

{

	writel(readl(DMAC_CONFIG(ch)) & ~DMAC_CONFIG_EN, DMAC_CONFIG(ch));

}



static inline void puv3_resume_dma(int ch)

{

	writel(readl(DMAC_CONFIG(ch)) | DMAC_CONFIG_EN, DMAC_CONFIG(ch));

}



#endif /* __MACH_PUV3_DMA_H__ */

arch/unicore32/include/mach/hardware.h

+1 −7
Original line number Diff line number Diff line
@@ -22,13 +22,7 @@ 


#ifndef __ASSEMBLY__



# define __REG(x)	(*((volatile unsigned long *)io_p2v(x)))

# define __PREG(x)	(io_v2p((unsigned long)&(x)))



#else



# define __REG(x)	io_p2v(x)

# define __PREG(x)	io_v2p(x)

# define __REG(x)	(void __iomem *)io_p2v(x)



#endif

arch/unicore32/kernel/clock.c

+18 −16
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ 
#include <linux/clk.h>

#include <linux/mutex.h>

#include <linux/delay.h>

#include <linux/io.h>



#include <mach/hardware.h>
@@ -152,28 +153,29 @@ int clk_set_rate(struct clk *clk, unsigned long rate) 
		if (ret)

			return ret;



		if (PM_PLLVGACFG == pll_vgacfg)

		if (readl(PM_PLLVGACFG) == pll_vgacfg)

			return 0;



		/* set pll vga cfg reg. */

		PM_PLLVGACFG = pll_vgacfg;

		writel(pll_vgacfg, PM_PLLVGACFG);



		PM_PMCR = PM_PMCR_CFBVGA;

		while ((PM_PLLDFCDONE & PM_PLLDFCDONE_VGADFC)

		writel(PM_PMCR_CFBVGA, PM_PMCR);

		while ((readl(PM_PLLDFCDONE) & PM_PLLDFCDONE_VGADFC)

				!= PM_PLLDFCDONE_VGADFC)

			udelay(100); /* about 1ms */



		/* set div cfg reg. */

		PM_PCGR |= PM_PCGR_VGACLK;

		writel(readl(PM_PCGR) | PM_PCGR_VGACLK, PM_PCGR);



		PM_DIVCFG = (PM_DIVCFG & ~PM_DIVCFG_VGACLK_MASK)

				| PM_DIVCFG_VGACLK(pll_vgadiv);

		writel((readl(PM_DIVCFG) & ~PM_DIVCFG_VGACLK_MASK)

				| PM_DIVCFG_VGACLK(pll_vgadiv), PM_DIVCFG);



		PM_SWRESET |= PM_SWRESET_VGADIV;

		while ((PM_SWRESET & PM_SWRESET_VGADIV) == PM_SWRESET_VGADIV)

		writel(readl(PM_SWRESET) | PM_SWRESET_VGADIV, PM_SWRESET);

		while ((readl(PM_SWRESET) & PM_SWRESET_VGADIV)

				== PM_SWRESET_VGADIV)

			udelay(100); /* 65536 bclk32, about 320us */



		PM_PCGR &= ~PM_PCGR_VGACLK;

		writel(readl(PM_PCGR) & ~PM_PCGR_VGACLK, PM_PCGR);

	}

#ifdef CONFIG_CPU_FREQ

	if (clk == &clk_mclk_clk) {
@@ -323,15 +325,15 @@ struct { 
static int __init clk_init(void)

{

#ifdef CONFIG_PUV3_PM

	u32 pllrate, divstatus = PM_DIVSTATUS;

	u32 pcgr_val = PM_PCGR;

	u32 pllrate, divstatus = readl(PM_DIVSTATUS);

	u32 pcgr_val = readl(PM_PCGR);

	int i;



	pcgr_val |= PM_PCGR_BCLKMME | PM_PCGR_BCLKH264E | PM_PCGR_BCLKH264D

			| PM_PCGR_HECLK | PM_PCGR_HDCLK;

	PM_PCGR = pcgr_val;

	writel(pcgr_val, PM_PCGR);



	pllrate = PM_PLLSYSSTATUS;

	pllrate = readl(PM_PLLSYSSTATUS);



	/* lookup pmclk_table */

	clk_mclk_clk.rate = 0;
@@ -346,7 +348,7 @@ static int __init clk_init(void) 
		clk_bclk32_clk.rate = clk_mclk_clk.rate /

			(((divstatus & 0x0000f000) >> 12) + 1);



	pllrate = PM_PLLDDRSTATUS;

	pllrate = readl(PM_PLLDDRSTATUS);



	/* lookup pddr_table */

	clk_ddr_clk.rate = 0;
@@ -357,7 +359,7 @@ static int __init clk_init(void) 
		}

	}



	pllrate = PM_PLLVGASTATUS;

	pllrate = readl(PM_PLLVGASTATUS);



	/* lookup pvga_table */

	clk_vga_clk.rate = 0;

arch/unicore32/kernel/dma.c

+9 −6
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ 
#include <linux/kernel.h>

#include <linux/interrupt.h>

#include <linux/errno.h>

#include <linux/io.h>



#include <asm/system.h>

#include <asm/irq.h>
@@ -94,15 +95,16 @@ EXPORT_SYMBOL(puv3_free_dma); 


static irqreturn_t dma_irq_handler(int irq, void *dev_id)

{

	int i, dint = DMAC_ITCSR;

	int i, dint;



	dint = readl(DMAC_ITCSR);

	for (i = 0; i < MAX_DMA_CHANNELS; i++) {

		if (dint & DMAC_CHANNEL(i)) {

			struct dma_channel *channel = &dma_channels[i];



			/* Clear TC interrupt of channel i */

			DMAC_ITCCR = DMAC_CHANNEL(i);

			DMAC_ITCCR = 0;

			writel(DMAC_CHANNEL(i), DMAC_ITCCR);

			writel(0, DMAC_ITCCR);



			if (channel->name && channel->irq_handler) {

				channel->irq_handler(i, channel->data);
@@ -121,15 +123,16 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id) 


static irqreturn_t dma_err_handler(int irq, void *dev_id)

{

	int i, dint = DMAC_IESR;

	int i, dint;



	dint = readl(DMAC_IESR);

	for (i = 0; i < MAX_DMA_CHANNELS; i++) {

		if (dint & DMAC_CHANNEL(i)) {

			struct dma_channel *channel = &dma_channels[i];



			/* Clear Err interrupt of channel i */

			DMAC_IECR = DMAC_CHANNEL(i);

			DMAC_IECR = 0;

			writel(DMAC_CHANNEL(i), DMAC_IECR);

			writel(0, DMAC_IECR);



			if (channel->name && channel->err_handler) {

				channel->err_handler(i, channel->data);