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Commit e571961e authored by Rajesh Kemisetti's avatar Rajesh Kemisetti
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ARM: dts: msm: Add GPU PIL for Zap shader on msmtitanium



GPU uses a zap shader ucode to flush internal memories when
switching from trusted to untrusted mode. This ucode needs to be
protected and programmed by the TZ. We use the PIL to do
the appropriate calls to the TZ for us and it needs a DT node
to recognize what needs to be loaded.

Change-Id: I83c06c86d41995cccc63b8283c589eea68fbb629
Signed-off-by: default avatarRajesh Kemisetti <rajeshk@codeaurora.org>
parent 1c10389d
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+16 −0
Original line number Diff line number Diff line
@@ -11,6 +11,22 @@
 */

&soc {
	pil_gpu: qcom,kgsl-hyp {
		compatible = "qcom,pil-tz-generic";
		qcom,pas-id = <13>;
		qcom,firmware-name = "a506_zap";
		memory-region = <&gpu_mem>;
		clocks = <&clock_gcc clk_gcc_crypto_clk>,
		<&clock_gcc clk_gcc_crypto_ahb_clk>,
		<&clock_gcc clk_gcc_crypto_axi_clk>,
		<&clock_gcc clk_crypto_clk_src>;
		clock-names = "scm_core_clk", "scm_iface_clk",
				"scm_bus_clk", "scm_core_clk_src";
		qcom,proxy-clock-names = "scm_core_clk", "scm_iface_clk",
				"scm_bus_clk", "scm_core_clk_src";
		qcom,scm_core_clk_src-freq = <80000000>;
	};

	msm_bus: qcom,kgsl-busmon {
		label = "kgsl-busmon";
		compatible = "qcom,kgsl-busmon";
+8 −0
Original line number Diff line number Diff line
@@ -80,6 +80,14 @@
			reg = <0x0 0x90000000 0x0 0x1400000>;
			label = "cont_splash_mem";
		};

		gpu_mem: gpu_region@0 {
			compatible = "shared-dma-pool";
			reusable;
			alloc-ranges = <0x0 0x80000000 0x0 0x10000000>;
			alignment = <0 0x400000>;
			size = <0 0x800000>;
		};
	};

	aliases {