Loading drivers/iommu/arm-smmu.c +20 −1 Original line number Diff line number Diff line Loading @@ -1468,7 +1468,9 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, } /* SCTLR */ reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP; reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_EAE_SBOP; if (!stage1 || !(smmu_domain->attributes & DOMAIN_ATTR_S1_BYPASS)) reg |= SCTLR_M; if (stage1) reg |= SCTLR_S1_ASIDPNE; #ifdef __BIG_ENDIAN Loading Loading @@ -2865,6 +2867,11 @@ static int arm_smmu_domain_get_attr(struct iommu_domain *domain, & (1 << DOMAIN_ATTR_NON_FATAL_FAULTS)); ret = 0; break; case DOMAIN_ATTR_S1_BYPASS: *((int *)data) = !!(smmu_domain->attributes & (1 << DOMAIN_ATTR_S1_BYPASS)); ret = 0; break; default: ret = -ENODEV; break; Loading Loading @@ -2976,6 +2983,18 @@ static int arm_smmu_domain_set_attr(struct iommu_domain *domain, smmu_domain->non_fatal_faults = *((int *)data); ret = 0; break; case DOMAIN_ATTR_S1_BYPASS: { int bypass = *((int *)data); if (bypass) smmu_domain->attributes |= 1 << DOMAIN_ATTR_S1_BYPASS; else smmu_domain->attributes &= ~(1 << DOMAIN_ATTR_S1_BYPASS); ret = 0; break; } default: ret = -ENODEV; break; Loading Loading
drivers/iommu/arm-smmu.c +20 −1 Original line number Diff line number Diff line Loading @@ -1468,7 +1468,9 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, } /* SCTLR */ reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP; reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_EAE_SBOP; if (!stage1 || !(smmu_domain->attributes & DOMAIN_ATTR_S1_BYPASS)) reg |= SCTLR_M; if (stage1) reg |= SCTLR_S1_ASIDPNE; #ifdef __BIG_ENDIAN Loading Loading @@ -2865,6 +2867,11 @@ static int arm_smmu_domain_get_attr(struct iommu_domain *domain, & (1 << DOMAIN_ATTR_NON_FATAL_FAULTS)); ret = 0; break; case DOMAIN_ATTR_S1_BYPASS: *((int *)data) = !!(smmu_domain->attributes & (1 << DOMAIN_ATTR_S1_BYPASS)); ret = 0; break; default: ret = -ENODEV; break; Loading Loading @@ -2976,6 +2983,18 @@ static int arm_smmu_domain_set_attr(struct iommu_domain *domain, smmu_domain->non_fatal_faults = *((int *)data); ret = 0; break; case DOMAIN_ATTR_S1_BYPASS: { int bypass = *((int *)data); if (bypass) smmu_domain->attributes |= 1 << DOMAIN_ATTR_S1_BYPASS; else smmu_domain->attributes &= ~(1 << DOMAIN_ATTR_S1_BYPASS); ret = 0; break; } default: ret = -ENODEV; break; Loading