Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit e4d2a598 authored by Anders Grafström's avatar Anders Grafström Committed by Russell King
Browse files

[ARM] 5310/1: Fix cache flush functions for ARMv4 



ARMv4 (ARM720T) cache flush functions are broken in 2.6.19+ kernels.
The issue was introduced by commit f12d0d7c
This patch corrects the CPU_CP15 ifdef statements so that they actually
do something.

Signed-off-by: default avatarAnders Grafström <grfstrm@users.sourceforge.net>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 957cf333

arch/arm/mm/cache-v4.S

+3 −3
Original line number Diff line number Diff line
@@ -29,7 +29,7 @@ ENTRY(v4_flush_user_cache_all) 
 *	Clean and invalidate the entire cache.

 */

ENTRY(v4_flush_kern_cache_all)

#ifdef CPU_CP15

#ifdef CONFIG_CPU_CP15

	mov	r0, #0

	mcr	p15, 0, r0, c7, c7, 0		@ flush ID cache

	mov	pc, lr
@@ -48,7 +48,7 @@ ENTRY(v4_flush_kern_cache_all) 
 *	- flags	- vma_area_struct flags describing address space

 */

ENTRY(v4_flush_user_cache_range)

#ifdef CPU_CP15

#ifdef CONFIG_CPU_CP15

	mov	ip, #0

	mcreq	p15, 0, ip, c7, c7, 0		@ flush ID cache

	mov	pc, lr
@@ -116,7 +116,7 @@ ENTRY(v4_dma_inv_range) 
 *	- end	 - virtual end address

 */

ENTRY(v4_dma_flush_range)

#ifdef CPU_CP15

#ifdef CONFIG_CPU_CP15

	mov	r0, #0

	mcr	p15, 0, r0, c7, c7, 0		@ flush ID cache

#endif