Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit e4ca4308 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'clk-for-linus-3.17' of git://git.linaro.org/people/mike.turquette/linux

Pull clock framework updates from Mike Turquette:
 "The clock framework changes for 3.17 are mostly additions of new clock
  drivers and fixes/enhancements to existing clock drivers.  There are
  also some non-critical fixes and improvements to the framework core.

  Changes to the clock framework core include:
   - improvements to printks on errors
   - flattening the previously hierarchal structure of per-clock entries
     in debugfs
   - allow per-clock debugfs entries that are specific to a particular
     clock driver
   - configure initial clock parent and/or initial clock rate from
     Device Tree
   - several feature enhancements to the composite clock type
   - misc fixes

  New clock drivers added include:
   - TI Palmas PMIC
   - Allwinner A23 SoC
   - Qualcomm APQ8084 and IPQ8064 SoCs
   - Rockchip rk3188, rk3066 and rk3288 SoCs
   - STMicroelectronics STiH407 SoC
   - Cirrus Logic CLPS711X SoC

  Many fixes, feature enhancements and further clock tree support for
  existing clock drivers also were merged, such as Samsung's "ARMCLK
  down" power saving feature for their Exynos4 & Exynos5 SoCs"

* tag 'clk-for-linus-3.17' of git://git.linaro.org/people/mike.turquette/linux: (86 commits)
  clk: Add missing of_clk_set_defaults export
  clk: checking wrong variable in __set_clk_parents()
  clk: Propagate any error return from debug_init()
  clk: clps711x: Add DT bindings documentation
  clk: Add CLPS711X clk driver
  clk: st: Use round to closest divider flag
  clk: st: Update frequency tables for fs660c32 and fs432c65
  clk: st: STiH407: Support for clockgenA9
  clk: st: STiH407: Support for clockgenD0/D2/D3
  clk: st: STiH407: Support for clockgenC0
  clk: st: Add quadfs reset handling
  clk: st: Add polarity bit indication
  clk: st: STiH407: Support for clockgenA0
  clk: st: STiH407: Support for A9 MUX Clocks
  clk: st: STiH407: Support for Flexgen Clocks
  clk: st: Adds Flexgen clock binding
  clk: st: Remove uncessary (void *) cast
  clk: st: use static const for clkgen_pll_data tables
  clk: st: use static const for stm_fs tables
  clk: st: Update ST clock binding documentation
  ...
parents e17acfdc b11a6fac
Loading
Loading
Loading
Loading
+30 −0
Original line number Diff line number Diff line
@@ -12,8 +12,38 @@ Properties:

 - reg : offset and length of the register set.

 - #clock-cells : must be <1>, since PMU requires once cell as clock specifier.
		The single specifier cell is used as index to list of clocks
		provided by PMU, which is currently:
			0 : SoC clock output (CLKOUT pin)

 - clock-names : list of clock names for particular CLKOUT mux inputs in
		following format:
			"clkoutN", where N is a decimal number corresponding to
			CLKOUT mux control bits value for given input, e.g.
				"clkout0", "clkout7", "clkout15".

 - clocks : list of phandles and specifiers to all input clocks listed in
		clock-names property.

Example :
pmu_system_controller: system-controller@10040000 {
	compatible = "samsung,exynos5250-pmu", "syscon";
	reg = <0x10040000 0x5000>;
	#clock-cells = <1>;
	clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
			"clkout4", "clkout8", "clkout9";
	clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
		<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
		<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,
		<&clock CLK_XUSBXTI>;
};

Example of clock consumer :

usb3503: usb3503@08 {
	/* ... */
	clock-names = "refclk";
	clocks = <&pmu_system_controller 0>;
	/* ... */
};
+35 −0
Original line number Diff line number Diff line
* Palmas 32KHz clocks *

Palmas device has two clock output pins for 32KHz, KG and KG_AUDIO.

This binding uses the common clock binding ./clock-bindings.txt.

Required properties:
- compatible :	"ti,palmas-clk32kg" for clk32kg clock
		"ti,palmas-clk32kgaudio" for clk32kgaudio clock
- #clock-cells : shall be set to 0.

Optional property:
- ti,external-sleep-control: The external enable input pins controlled the
	enable/disable of clocks.  The external enable input pins ENABLE1,
	ENABLE2 and NSLEEP. The valid values for the external pins are:
		PALMAS_EXT_CONTROL_PIN_ENABLE1 for ENABLE1 pin
		PALMAS_EXT_CONTROL_PIN_ENABLE2 for ENABLE2 pin
		PALMAS_EXT_CONTROL_PIN_NSLEEP for NSLEEP pin
	Option 0 or missing this property means the clock is enabled/disabled
	via register access and these pins do not have any control.
	The macros of external control pins for DTS is defined at
	dt-bindings/mfd/palmas.h

Example:
	#include <dt-bindings/mfd/palmas.h>
	...
	palmas: tps65913@58 {
		...
		clk32kg: palmas_clk32k@0 {
			compatible = "ti,palmas-clk32kg";
			#clock-cells = <0>;
			ti,external-sleep-control = <PALMAS_EXT_CONTROL_PIN_NSLEEP>;
		};
		...
	};
+36 −0
Original line number Diff line number Diff line
@@ -131,3 +131,39 @@ clock signal, and a UART.
  ("pll" and "pll-switched").
* The UART has its baud clock connected the external oscillator and its
  register clock connected to the PLL clock (the "pll-switched" signal)

==Assigned clock parents and rates==

Some platforms may require initial configuration of default parent clocks
and clock frequencies. Such a configuration can be specified in a device tree
node through assigned-clocks, assigned-clock-parents and assigned-clock-rates
properties. The assigned-clock-parents property should contain a list of parent
clocks in form of phandle and clock specifier pairs, the assigned-clock-parents
property the list of assigned clock frequency values - corresponding to clocks
listed in the assigned-clocks property.

To skip setting parent or rate of a clock its corresponding entry should be
set to 0, or can be omitted if it is not followed by any non-zero entry.

    uart@a000 {
        compatible = "fsl,imx-uart";
        reg = <0xa000 0x1000>;
        ...
        clocks = <&osc 0>, <&pll 1>;
        clock-names = "baud", "register";

        assigned-clocks = <&clkcon 0>, <&pll 2>;
        assigned-clock-parents = <&pll 2>;
        assigned-clock-rates = <0>, <460800>;
    };

In this example the <&pll 2> clock is set as parent of clock <&clkcon 0> and
the <&pll 2> clock is assigned a frequency value of 460800 Hz.

Configuring a clock's parent and rate through the device node that consumes
the clock can be done only for clocks that have a single user. Specifying
conflicting parent or rate configuration in multiple consumer nodes for
a shared clock is forbidden.

Configuration of common clocks, which affect multiple consumer devices can
be similarly specified in the clock provider node.
+19 −0
Original line number Diff line number Diff line
* Clock bindings for the Cirrus Logic CLPS711X CPUs

Required properties:
- compatible       : Shall contain "cirrus,clps711x-clk".
- reg              : Address of the internal register set.
- startup-frequency: Factory set CPU startup frequency in HZ.
- #clock-cells     : Should be <1>.

The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/clps711x-clock.h
for the full list of CLPS711X clock IDs.

Example:
	clks: clks@80000000 {
		#clock-cells = <1>;
		compatible = "cirrus,ep7312-clk", "cirrus,clps711x-clk";
		reg = <0x80000000 0xc000>;
		startup-frequency = <73728000>;
	};
+2 −0
Original line number Diff line number Diff line
@@ -5,6 +5,8 @@ Required properties :
- compatible : shall contain only one of the following:

			"qcom,gcc-apq8064"
			"qcom,gcc-apq8084"
			"qcom,gcc-ipq8064"
			"qcom,gcc-msm8660"
			"qcom,gcc-msm8960"
			"qcom,gcc-msm8974"
Loading