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Commit e47380bd authored by Haritha Avadanam's avatar Haritha Avadanam
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ARM: dts: msm: Add qcedev, qcrypto nodes to MDM9650 



On MDM9650, to enable qceddev, qcrypto drivers, add
qcedev and qcrypto nodes to MDM9650 device tree.

Change-Id: I1c950aff6ce1cd4b8492ef5b30181b73a86a53db
Signed-off-by: default avatarHaritha Avadanam <havada@codeaurora.org>
parent 2dc2816f

arch/arm/boot/dts/qcom/mdm9650.dtsi

+58 −0
Original line number Diff line number Diff line
@@ -533,6 +533,64 @@ 
		clock-names = "iface_clk";

	};



	qcom,qcedev@720000 {

		compatible = "qcom,qcedev";

		reg = <0x720000 0x20000>,

			<0x704000 0x20000>;

		reg-names = "crypto-base","crypto-bam-base";

		interrupts = <0 207 0>;

		qcom,bam-pipe-pair = <1>;

		qcom,ce-hw-instance = <0>;

		qcom,ce-device = <0>;

		qcom,ce-hw-shared;

		qcom,msm-bus,name = "qcedev-noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

			<47 512 0 0>,

			<47 512 393600 393600>;

		clocks =

			<&clock_gcc clk_qcedev_ce_clk>,

			<&clock_gcc clk_qcedev_ce_clk>,

			<&clock_gcc clk_qcedev_ce_clk>,

			<&clock_gcc clk_qcedev_ce_clk>;

		clock-names = "core_clk", "iface_clk",

			"bus_clk","core_clk_src";

		qcom,ce-opp-freq = <171430000>;

	};



	qcom,qcrypto@720000 {

		compatible = "qcom,qcrypto";

		reg = <0x720000 0x20000>,

			<0x704000 0x20000>;

		reg-names = "crypto-base","crypto-bam-base";

		interrupts = <0 207 0>;

		qcom,bam-pipe-pair = <2>;

		qcom,ce-hw-instance = <0>;

		qcom,ce-device = <0>;

		qcom,ce-hw-shared;

		qcom,msm-bus,name = "qcrypto-noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

			<47 512 0 0>,

			<47 512 393600 393600>;

		clocks =

			<&clock_gcc clk_qcedev_ce_clk>,

			<&clock_gcc clk_qcedev_ce_clk>,

			<&clock_gcc clk_qcedev_ce_clk>,

			<&clock_gcc clk_qcedev_ce_clk>;

		clock-names = "core_clk", "iface_clk",

			"bus_clk","core_clk_src";

		qcom,use-sw-aes-cbc-ecb-ctr-algo;

		qcom,use-sw-aes-xts-algo;

		qcom,use-sw-aes-ccm-algo;

		qcom,use-sw-ahash-algo;

		qcom,use-sw-hmac-algo;

		qcom,use-sw-aead-algo;

		qcom,ce-opp-freq = <171430000>;

	};



	qcom,rmnet-ipa {

		compatible = "qcom,rmnet-ipa3";

		qcom,rmnet-ipa-ssr;