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Commit e3deb204 authored by Eric Anholt's avatar Eric Anholt
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agp/intel: Use a non-reserved value for the cache field of the PTEs. 



I don't know if this is what we'll want to be using long term, we'll see.

Signed-off-by: default avatarEric Anholt <eric@anholt.net>
parent f6e450a6

drivers/char/agp/intel-agp.c

+5 −0
Original line number Diff line number Diff line
@@ -296,6 +296,11 @@ static void intel_agp_insert_sg_entries(struct agp_memory *mem, 
					off_t pg_start, int mask_type)

{

	int i, j;

	u32 cache_bits = 0;



	if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB) {

		cache_bits = I830_PTE_SYSTEM_CACHED;

	}



	for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {

		writel(agp_bridge->driver->mask_memory(agp_bridge,