Commit e3432593 authored Jan 20, 2015 by Mitchel Humpherys Committed by Matt Wagantall May 30, 2015

iommu/arm-smmu: use outer cacheability for coherent table walks



Currently we're setting page table cacheability to "inner shareable"
when coherent table walking is enabled, but it should actually be "outer
shareable".  Fix this.

Change-Id: I7939bb75da8327f01a2fcd941a0d8358de6f0bc5
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>

parent 4d9088b0

drivers/iommu/arm-smmu.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -1066,7 +1066,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
		reg \|= TTBCR_EAE;

		if (!coherent_htw_disable) {
		reg \|= (TTBCR_SH_IS << TTBCR_SH0_SHIFT) \|
		reg \|= (TTBCR_SH_OS << TTBCR_SH0_SHIFT) \|
		(TTBCR_RGN_WBWA << TTBCR_ORGN0_SHIFT) \|
		(TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT);
		}