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Commit e319e765 authored by Robert Richter's avatar Robert Richter Committed by Ingo Molnar
Browse files

x86: apic: extended interrupt LVT support for AMD 



Signed-off-by: default avatarRobert Richter <robert.richter@amd.com>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent 04adf114

arch/x86/kernel/apic_32.c

+29 −0
Original line number Diff line number Diff line
@@ -620,6 +620,35 @@ int setup_profiling_timer(unsigned int multiplier) 
	return -EINVAL;

}



/*

 * Setup extended LVT, AMD specific (K8, family 10h)

 *

 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and

 * MCE interrupts are supported. Thus MCE offset must be set to 0.

 */



#define APIC_EILVT_LVTOFF_MCE 0

#define APIC_EILVT_LVTOFF_IBS 1



static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)

{

	unsigned long reg = (lvt_off << 4) + APIC_EILVT0;

	unsigned int  v   = (mask << 16) | (msg_type << 8) | vector;

	apic_write(reg, v);

}



u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)

{

	setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);

	return APIC_EILVT_LVTOFF_MCE;

}



u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)

{

	setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);

	return APIC_EILVT_LVTOFF_IBS;

}



/*

 * Local APIC start and shutdown

 */