Merge branch 'mb862xxfb-for-next' of git://git.denx.de/linux-2.6-agust (e2968f70) · Commits · e / devices / android_kernel_xiaomi_markw

drivers/video/Kconfig

+9 −0

Original line number	Diff line number	Diff line
		@@ -2294,6 +2294,15 @@ config FB_MB862XX_LIME

		endchoice

		config FB_MB862XX_I2C
		bool "Support I2C bus on MB862XX GDC"
		depends on FB_MB862XX && I2C
		default y
		help
		Selecting this option adds Coral-P(A)/Lime GDC I2C bus adapter
		driver to support accessing I2C devices on controller's I2C bus.
		These are usually some video decoder chips.

		config FB_EP93XX
		tristate "EP93XX frame buffer support"
		depends on FB && ARCH_EP93XX

drivers/video/mb862xx/Makefile

+4 −1

Original line number	Diff line number	Diff line
		@@ -2,4 +2,7 @@
		# Makefile for the MB862xx framebuffer driver
		#

		obj-$(CONFIG_FB_MB862XX) := mb862xxfb.o mb862xxfb_accel.o
		obj-$(CONFIG_FB_MB862XX) += mb862xxfb.o

		mb862xxfb-y := mb862xxfbdrv.o mb862xxfb_accel.o
		mb862xxfb-$(CONFIG_FB_MB862XX_I2C) += mb862xx-i2c.o

drivers/video/mb862xx/mb862xx-i2c.c

0 → 100644

+177 −0

Original line number	Diff line number	Diff line
		/*
		* Coral-P(A)/Lime I2C adapter driver
		*
		* (C) 2011 DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 as
		* published by the Free Software Foundation.
		*
		*/

		#include <linux/fb.h>
		#include <linux/i2c.h>
		#include <linux/io.h>

		#include "mb862xxfb.h"
		#include "mb862xx_reg.h"

		static int mb862xx_i2c_wait_event(struct i2c_adapter *adap)
		{
		struct mb862xxfb_par *par = adap->algo_data;
		u32 reg;

		do {
		udelay(1);
		reg = inreg(i2c, GC_I2C_BCR);
		if (reg & (I2C_INT \| I2C_BER))
		break;
		} while (1);

		return (reg & I2C_BER) ? 0 : 1;
		}

		static int mb862xx_i2c_do_address(struct i2c_adapter *adap, int addr)
		{
		struct mb862xxfb_par *par = adap->algo_data;

		outreg(i2c, GC_I2C_DAR, addr);
		outreg(i2c, GC_I2C_CCR, I2C_CLOCK_AND_ENABLE);
		outreg(i2c, GC_I2C_BCR, par->i2c_rs ? I2C_REPEATED_START : I2C_START);
		if (!mb862xx_i2c_wait_event(adap))
		return -EIO;
		par->i2c_rs = !(inreg(i2c, GC_I2C_BSR) & I2C_LRB);
		return par->i2c_rs;
		}

		static int mb862xx_i2c_write_byte(struct i2c_adapter *adap, u8 byte)
		{
		struct mb862xxfb_par *par = adap->algo_data;

		outreg(i2c, GC_I2C_DAR, byte);
		outreg(i2c, GC_I2C_BCR, I2C_START);
		if (!mb862xx_i2c_wait_event(adap))
		return -EIO;
		return !(inreg(i2c, GC_I2C_BSR) & I2C_LRB);
		}

		static int mb862xx_i2c_read_byte(struct i2c_adapter adap, u8 byte, int last)
		{
		struct mb862xxfb_par *par = adap->algo_data;

		outreg(i2c, GC_I2C_BCR, I2C_START \| (last ? 0 : I2C_ACK));
		if (!mb862xx_i2c_wait_event(adap))
		return 0;
		*byte = inreg(i2c, GC_I2C_DAR);
		return 1;
		}

		void mb862xx_i2c_stop(struct i2c_adapter *adap)
		{
		struct mb862xxfb_par *par = adap->algo_data;

		outreg(i2c, GC_I2C_BCR, I2C_STOP);
		outreg(i2c, GC_I2C_CCR, I2C_DISABLE);
		par->i2c_rs = 0;
		}

		static int mb862xx_i2c_read(struct i2c_adapter adap, struct i2c_msg m)
		{
		int i, ret = 0;
		int last = m->len - 1;

		for (i = 0; i < m->len; i++) {
		if (!mb862xx_i2c_read_byte(adap, &m->buf[i], i == last)) {
		ret = -EIO;
		break;
		}
		}
		return ret;
		}

		static int mb862xx_i2c_write(struct i2c_adapter adap, struct i2c_msg m)
		{
		int i, ret = 0;

		for (i = 0; i < m->len; i++) {
		if (!mb862xx_i2c_write_byte(adap, m->buf[i])) {
		ret = -EIO;
		break;
		}
		}
		return ret;
		}

		static int mb862xx_xfer(struct i2c_adapter adap, struct i2c_msg msgs,
		int num)
		{
		struct mb862xxfb_par *par = adap->algo_data;
		struct i2c_msg *m;
		int addr;
		int i = 0, err = 0;

		dev_dbg(par->dev, "%s: %d msgs\n", __func__, num);

		for (i = 0; i < num; i++) {
		m = &msgs[i];
		if (!m->len) {
		dev_dbg(par->dev, "%s: null msgs\n", __func__);
		continue;
		}
		addr = m->addr;
		if (m->flags & I2C_M_RD)
		addr \|= 1;

		err = mb862xx_i2c_do_address(adap, addr);
		if (err < 0)
		break;
		if (m->flags & I2C_M_RD)
		err = mb862xx_i2c_read(adap, m);
		else
		err = mb862xx_i2c_write(adap, m);
		}

		if (i)
		mb862xx_i2c_stop(adap);

		return (err < 0) ? err : i;
		}

		static u32 mb862xx_func(struct i2c_adapter *adap)
		{
		return I2C_FUNC_SMBUS_BYTE_DATA;
		}

		static const struct i2c_algorithm mb862xx_algo = {
		.master_xfer = mb862xx_xfer,
		.functionality = mb862xx_func,
		};

		static struct i2c_adapter mb862xx_i2c_adapter = {
		.name = "MB862xx I2C adapter",
		.algo = &mb862xx_algo,
		.owner = THIS_MODULE,
		};

		int mb862xx_i2c_init(struct mb862xxfb_par *par)
		{
		int ret;

		mb862xx_i2c_adapter.algo_data = par;
		par->adap = &mb862xx_i2c_adapter;

		ret = i2c_add_adapter(par->adap);
		if (ret < 0) {
		dev_err(par->dev, "failed to add %s\n",
		mb862xx_i2c_adapter.name);
		}
		return ret;
		}

		void mb862xx_i2c_exit(struct mb862xxfb_par *par)
		{
		if (par->adap) {
		i2c_del_adapter(par->adap);
		par->adap = NULL;
		}
		}

drivers/video/mb862xx/mb862xx_reg.h

+54 −4

Original line number	Diff line number	Diff line
		@@ -5,11 +5,8 @@
		#ifndef _MB862XX_REG_H
		#define _MB862XX_REG_H

		#ifdef MB862XX_MMIO_BOTTOM
		#define MB862XX_MMIO_BASE 0x03fc0000
		#else
		#define MB862XX_MMIO_BASE 0x01fc0000
		#endif
		#define MB862XX_MMIO_HIGH_BASE 0x03fc0000
		#define MB862XX_I2C_BASE 0x0000c000
		#define MB862XX_DISP_BASE 0x00010000
		#define MB862XX_CAP_BASE 0x00018000
		@@ -23,6 +20,7 @@
		#define GC_IMASK 0x00000024
		#define GC_SRST 0x0000002c
		#define GC_CCF 0x00000038
		#define GC_RSW 0x0000005c
		#define GC_CID 0x000000f0
		#define GC_REVISION 0x00000084

		@@ -53,10 +51,16 @@
		#define GC_L0OA0 0x00000024
		#define GC_L0DA0 0x00000028
		#define GC_L0DY_L0DX 0x0000002c
		#define GC_L1M 0x00000030
		#define GC_L1DA 0x00000034
		#define GC_DCM1 0x00000100
		#define GC_L0EM 0x00000110
		#define GC_L0WY_L0WX 0x00000114
		#define GC_L0WH_L0WW 0x00000118
		#define GC_L1EM 0x00000120
		#define GC_L1WY_L1WX 0x00000124
		#define GC_L1WH_L1WW 0x00000128
		#define GC_DLS 0x00000180
		#define GC_DCM2 0x00000104
		#define GC_DCM3 0x00000108
		#define GC_CPM_CUTC 0x000000a0
		@@ -68,6 +72,11 @@

		#define GC_CPM_CEN0 0x00100000
		#define GC_CPM_CEN1 0x00200000
		#define GC_DCM1_DEN 0x80000000
		#define GC_DCM1_L1E 0x00020000
		#define GC_L1M_16 0x80000000
		#define GC_L1M_YC 0x40000000
		#define GC_L1M_CS 0x20000000

		#define GC_DCM01_ESY 0x00000004
		#define GC_DCM01_SC 0x00003f00
		@@ -79,9 +88,50 @@
		#define GC_L0M_L0C_16 0x80000000
		#define GC_L0EM_L0EC_24 0x40000000
		#define GC_L0M_L0W_UNIT 64
		#define GC_L1EM_DM 0x02000000

		#define GC_DISP_REFCLK_400 400

		/* I2C */
		#define GC_I2C_BSR 0x00000000 /* BSR */
		#define GC_I2C_BCR 0x00000004 /* BCR */
		#define GC_I2C_CCR 0x00000008 /* CCR */
		#define GC_I2C_ADR 0x0000000C /* ADR */
		#define GC_I2C_DAR 0x00000010 /* DAR */

		#define I2C_DISABLE 0x00000000
		#define I2C_STOP 0x00000000
		#define I2C_START 0x00000010
		#define I2C_REPEATED_START 0x00000030
		#define I2C_CLOCK_AND_ENABLE 0x0000003f
		#define I2C_READY 0x01
		#define I2C_INT 0x01
		#define I2C_INTE 0x02
		#define I2C_ACK 0x08
		#define I2C_BER 0x80
		#define I2C_BEIE 0x40
		#define I2C_TRX 0x80
		#define I2C_LRB 0x10

		/* Capture registers and bits */
		#define GC_CAP_VCM 0x00000000
		#define GC_CAP_CSC 0x00000004
		#define GC_CAP_VCS 0x00000008
		#define GC_CAP_CBM 0x00000010
		#define GC_CAP_CBOA 0x00000014
		#define GC_CAP_CBLA 0x00000018
		#define GC_CAP_IMG_START 0x0000001C
		#define GC_CAP_IMG_END 0x00000020
		#define GC_CAP_CMSS 0x00000048
		#define GC_CAP_CMDS 0x0000004C

		#define GC_VCM_VIE 0x80000000
		#define GC_VCM_CM 0x03000000
		#define GC_VCM_VS_PAL 0x00000002
		#define GC_CBM_OO 0x80000000
		#define GC_CBM_HRV 0x00000010
		#define GC_CBM_CBST 0x00000001

		/* Carmine specific */
		#define MB86297_DRAW_BASE 0x00020000
		#define MB86297_DISP0_BASE 0x00100000

drivers/video/mb862xx/mb862xxfb.h

+36 −0

Original line number	Diff line number	Diff line
		#ifndef __MB862XX_H__
		#define __MB862XX_H__

		struct mb862xx_l1_cfg {
		unsigned short sx;
		unsigned short sy;
		unsigned short sw;
		unsigned short sh;
		unsigned short dx;
		unsigned short dy;
		unsigned short dw;
		unsigned short dh;
		int mirror;
		};

		#define MB862XX_BASE 'M'
		#define MB862XX_L1_GET_CFG _IOR(MB862XX_BASE, 0, struct mb862xx_l1_cfg*)
		#define MB862XX_L1_SET_CFG _IOW(MB862XX_BASE, 1, struct mb862xx_l1_cfg*)
		#define MB862XX_L1_ENABLE _IOW(MB862XX_BASE, 2, int)
		#define MB862XX_L1_CAP_CTL _IOW(MB862XX_BASE, 3, int)

		#ifdef __KERNEL__

		#define PCI_VENDOR_ID_FUJITSU_LIMITED 0x10cf
		#define PCI_DEVICE_ID_FUJITSU_CORALP 0x2019
		#define PCI_DEVICE_ID_FUJITSU_CORALPA 0x201e
		@@ -38,6 +58,8 @@ struct mb862xxfb_par {
		void __iomem mmio_base; / remapped registers */
		size_t mapped_vram; /* length of remapped vram */
		size_t mmio_len; /* length of register region */
		unsigned long cap_buf; /* capture buffers offset */
		size_t cap_len; /* length of capture buffers */

		void __iomem host; / relocatable reg. bases */
		void __iomem *i2c;
		@@ -57,11 +79,23 @@ struct mb862xxfb_par {
		unsigned int refclk; /* disp. reference clock */
		struct mb862xx_gc_mode gc_mode; / GDC mode init data */
		int pre_init; /* don't init display if 1 */
		struct i2c_adapter adap; / GDC I2C bus adapter */
		int i2c_rs;

		struct mb862xx_l1_cfg l1_cfg;
		int l1_stride;

		u32 pseudo_palette[16];
		};

		extern void mb862xxfb_init_accel(struct fb_info *info, int xres);
		#ifdef CONFIG_FB_MB862XX_I2C
		extern int mb862xx_i2c_init(struct mb862xxfb_par *par);
		extern void mb862xx_i2c_exit(struct mb862xxfb_par *par);
		#else
		static inline int mb862xx_i2c_init(struct mb862xxfb_par *par) { return 0; }
		static inline void mb862xx_i2c_exit(struct mb862xxfb_par *par) { }
		#endif

		#if defined(CONFIG_FB_MB862XX_LIME) && defined(CONFIG_FB_MB862XX_PCI_GDC)
		#error "Select Lime GDC or CoralP/Carmine support, but not both together"
		@@ -82,4 +116,6 @@ extern void mb862xxfb_init_accel(struct fb_info *info, int xres);

		#define pack(a, b) (((a) << 16) \| (b))

		#endif /* __KERNEL__ */

		#endif