Merge "ARM: dts: msm: enable high speed uart driver for apq8009"

};

/delete-node/ &cont_splash_mem;

&msm_gpio{

	hsuart_active: default {

		mux {

			pins = "gpio20", "gpio21", "gpio111", "gpio112";

			function = "blsp_uart2";

		};

		config {

			pins = "gpio20", "gpio21", "gpio111", "gpio112";

			drive-strength = <16>;

			bias-disable;

		};

	};

	hsuart_sleep: sleep {

		mux {

			pins = "gpio20", "gpio21", "gpio111", "gpio112";

			function = "blsp_uart2";

		};

		config {

			pins = "gpio20", "gpio21", "gpio111", "gpio112";

			drive-strength = <2>;

			bias-disable;

		};

	};

};

&soc{

	blsp1_uart2_hs: uart@78b0000 {

		compatible = "qcom,msm-hsuart-v14";

		reg = <0x78b0000 0x200>,

			<0x7884000 0x1f000>;

		reg-names = "core_mem", "bam_mem";

		interrupt-names = "core_irq", "bam_irq";

		#address-cells = <0>;

		interrupt-parent = <&blsp1_uart2_hs>;

		interrupts = <0 1>;

		#interrupt-cells = <1>;

		interrupt-map-mask = <0xffffffff>;

		interrupt-map = <0 &intc 0 108 0

				1 &intc 0 238 0>;

		qcom,inject-rx-on-wakeup;

		qcom,rx-char-to-inject = <0xfd>;

		qcom,master-id = <86>;

		clock-names = "core_clk", "iface_clk";

		clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>,

				<&clock_gcc clk_gcc_blsp1_ahb_clk>;

		pinctrl-names = "sleep", "default";

		pinctrl-0 = <&hsuart_sleep>;

		pinctrl-1 = <&hsuart_active>;

		qcom,bam-tx-ep-pipe-index = <2>;

		qcom,bam-rx-ep-pipe-index = <3>;

		qcom,msm-bus,name = "blsp1_uart2_hs";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<86 512 0 0>,

				<86 512 500 800>;

		status = "ok";

	};

};