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Commit e25cdf90 authored by Deepak Katragadda's avatar Deepak Katragadda
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clk: msm: clock-mmss-8996: Update the fmax values for MMPLL2 and MMPLL8 



Update the MMPLL2 and MMPLL8 fmax levels to align with the
spark PLL datasheet recommendations.

Change-Id: I8e6e4293d802707fd8a1dd0482bea24a3030683b
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent 30955ba1

drivers/clk/msm/clock-mmss-8996.c

+8 −8
Original line number Diff line number Diff line
@@ -3280,10 +3280,10 @@ static void msm_mmsscc_8996_v2_fixup(void) 
	mmpll2.vco_tbl = mmpll_gfx_vco;

	mmpll2.num_vco = ARRAY_SIZE(mmpll_gfx_vco),

	mmpll2.c.rate = 0;

	mmpll2.c.fmax[VDD_DIG_LOWER] = 650000000;

	mmpll2.c.fmax[VDD_DIG_LOW] = 650000000;

	mmpll2.c.fmax[VDD_DIG_NOMINAL] = 1300000000;

	mmpll2.c.fmax[VDD_DIG_HIGH] = 1300000000;

	mmpll2.c.fmax[VDD_DIG_LOWER] = 1000000000;

	mmpll2.c.fmax[VDD_DIG_LOW] = 1000000000;

	mmpll2.c.fmax[VDD_DIG_NOMINAL] = 1000000000;

	mmpll2.c.fmax[VDD_DIG_HIGH] = 1000000000;

	mmpll2.no_prepared_reconfig = true;

	mmpll2.c.ops = &clk_ops_alpha_pll;
@@ -3307,10 +3307,10 @@ static void msm_mmsscc_8996_v2_fixup(void) 
	mmpll8.vco_tbl = mmpll_gfx_vco;

	mmpll8.num_vco = ARRAY_SIZE(mmpll_gfx_vco),

	mmpll8.c.rate = 0;

	mmpll8.c.fmax[VDD_DIG_LOWER] = 650000000;

	mmpll8.c.fmax[VDD_DIG_LOW] = 650000000;

	mmpll8.c.fmax[VDD_DIG_NOMINAL] = 1300000000;

	mmpll8.c.fmax[VDD_DIG_HIGH] = 1300000000;

	mmpll8.c.fmax[VDD_DIG_LOWER] = 1000000000;

	mmpll8.c.fmax[VDD_DIG_LOW] = 1000000000;

	mmpll8.c.fmax[VDD_DIG_NOMINAL] = 1000000000;

	mmpll8.c.fmax[VDD_DIG_HIGH] = 1000000000;

	mmpll8.no_prepared_reconfig = true;

	mmpll8.c.ops = &clk_ops_alpha_pll;