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Commit e252d07a authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: rip out gen2 reset code 



At least on my i830M here it reliably results in hard system hangs
nowadays. This is much worse than falling back to software rendering,
so I think we should simply rip this out.

After all we don't have any gpu reset for gen3 either, and there are a
lot more of those still around.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 3bbbe706

drivers/gpu/drm/i915/intel_uncore.c

+0 −31
Original line number Diff line number Diff line
@@ -490,36 +490,6 @@ int i915_reg_read_ioctl(struct drm_device *dev, 
	return 0;

}



static int i8xx_do_reset(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;



	if (IS_I85X(dev))

		return -ENODEV;



	I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);

	POSTING_READ(D_STATE);



	if (IS_I830(dev) || IS_845G(dev)) {

		I915_WRITE(DEBUG_RESET_I830,

			   DEBUG_RESET_DISPLAY |

			   DEBUG_RESET_RENDER |

			   DEBUG_RESET_FULL);

		POSTING_READ(DEBUG_RESET_I830);

		msleep(1);



		I915_WRITE(DEBUG_RESET_I830, 0);

		POSTING_READ(DEBUG_RESET_I830);

	}



	msleep(1);



	I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);

	POSTING_READ(D_STATE);



	return 0;

}



static int i965_reset_complete(struct drm_device *dev)

{

	u8 gdrst;
@@ -621,7 +591,6 @@ int intel_gpu_reset(struct drm_device *dev) 
	case 6: return gen6_do_reset(dev);

	case 5: return ironlake_do_reset(dev);

	case 4: return i965_do_reset(dev);

	case 2: return i8xx_do_reset(dev);

	default: return -ENODEV;

	}

}