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Commit e1ef7cc2 authored by Ben Widawsky's avatar Ben Widawsky Committed by Daniel Vetter
Browse files

drm/i915: Macro to determine DPF support 



Originally I had a macro specifically for DPF support, and Daniel, with
good reason asked me to change it to this. It's not the way I would have
gone (and indeed I didn't), but for now there is no distinction as all
platforms with L3 also have DPF.

Note: The good reasons are that dpf is a l3$ feature (at least on
currrent hw), hence I don't expect one to go without the other.

Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
[danvet: added note]
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 2e4291e0

drivers/gpu/drm/i915/i915_drv.h

+2 −0
Original line number Diff line number Diff line
@@ -1114,6 +1114,8 @@ struct drm_i915_file_private { 


#define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)



#define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev))



#include "i915_trace.h"



/**

drivers/gpu/drm/i915/i915_irq.c

+1 −1
Original line number Diff line number Diff line
@@ -444,7 +444,7 @@ static void ivybridge_handle_parity_error(struct drm_device *dev) 
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;

	unsigned long flags;



	if (!IS_IVYBRIDGE(dev))

	if (!HAS_L3_GPU_CACHE(dev))

		return;



	spin_lock_irqsave(&dev_priv->irq_lock, flags);

drivers/gpu/drm/i915/i915_sysfs.c

+1 −1
Original line number Diff line number Diff line
@@ -212,7 +212,7 @@ void i915_setup_sysfs(struct drm_device *dev) 
			DRM_ERROR("RC6 residency sysfs setup failed\n");

	}



	if (IS_IVYBRIDGE(dev)) {

	if (HAS_L3_GPU_CACHE(dev)) {

		ret = device_create_bin_file(&dev->primary->kdev, &dpf_attrs);

		if (ret)

			DRM_ERROR("l3 parity sysfs setup failed\n");

drivers/gpu/drm/i915/intel_ringbuffer.c

+3 −3
Original line number Diff line number Diff line
@@ -454,7 +454,7 @@ static int init_render_ring(struct intel_ring_buffer *ring) 
	if (INTEL_INFO(dev)->gen >= 6)

		I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));



	if (IS_IVYBRIDGE(dev))

	if (HAS_L3_GPU_CACHE(dev))

		I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);



	return ret;
@@ -844,7 +844,7 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring) 


	spin_lock_irqsave(&dev_priv->irq_lock, flags);

	if (ring->irq_refcount++ == 0) {

		if (IS_IVYBRIDGE(dev) && ring->id == RCS)

		if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)

			I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |

						GEN6_RENDER_L3_PARITY_ERROR));

		else
@@ -867,7 +867,7 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring) 


	spin_lock_irqsave(&dev_priv->irq_lock, flags);

	if (--ring->irq_refcount == 0) {

		if (IS_IVYBRIDGE(dev) && ring->id == RCS)

		if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)

			I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);

		else

			I915_WRITE_IMR(ring, ~0);