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Commit e1c96c86 authored by Florian Fainelli's avatar Florian Fainelli Committed by Ralf Baechle
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MIPS: BCM63xx: Remove BCM6345 hacks to read base boot address 



Though BCM6345 does not technically have the same MPI register layout
than the other SoCs, reading the chip-select registers is done the same
way, and particularly for chip-select 0, which is the boot flash.

Signed-off-by: default avatarFlorian Fainelli <florian@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3009/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent d61fcfe2

arch/mips/bcm63xx/boards/board_bcm963xx.c

+6 −15
Original line number Diff line number Diff line
@@ -709,15 +709,9 @@ void __init board_prom_init(void) 
	char cfe_version[32];

	u32 val;



	/* read base address of boot chip select (0)

	 * 6345 does not have MPI but boots from standard

	 * MIPS Flash address */

	if (BCMCPU_IS_6345())

		val = 0x1fc00000;

	else {

	/* read base address of boot chip select (0) */

	val = bcm_mpi_readl(MPI_CSBASE_REG(0));

	val &= MPI_CSBASE_BASE_MASK;

	}

	boot_addr = (u8 *)KSEG1ADDR(val);



	/* dump cfe version */
@@ -893,12 +887,9 @@ int __init board_register_devices(void) 
		bcm63xx_dsp_register(&board.dsp);



	/* read base address of boot chip select (0) */

	if (BCMCPU_IS_6345())

		val = 0x1fc00000;

	else {

	val = bcm_mpi_readl(MPI_CSBASE_REG(0));

	val &= MPI_CSBASE_BASE_MASK;

	}



	mtd_resources[0].start = val;

	mtd_resources[0].end = 0x1FFFFFFF;

arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h

+1 −1
Original line number Diff line number Diff line
@@ -215,7 +215,7 @@ enum bcm63xx_regs_set { 
#define BCM_6345_ENETDMAS_BASE		(0xfffe2a00)

#define BCM_6345_ENETSW_BASE		(0xdeadbeef)

#define BCM_6345_PCMCIA_BASE		(0xfffe2028)

#define BCM_6345_MPI_BASE		(0xdeadbeef)

#define BCM_6345_MPI_BASE		(0xfffe2000)

#define BCM_6345_OHCI0_BASE		(0xfffe2100)

#define BCM_6345_OHCI_PRIV_BASE		(0xfffe2200)

#define BCM_6345_USBH_PRIV_BASE		(0xdeadbeef)