Loading drivers/gpu/msm/adreno.c +2 −0 Original line number Diff line number Diff line Loading @@ -1544,6 +1544,8 @@ static int adreno_stop(struct kgsl_device *device) adreno_ringbuffer_stop(adreno_dev); kgsl_pwrscale_update_stats(device); adreno_irqctrl(adreno_dev, 0); adreno_ocmem_free(adreno_dev); Loading drivers/gpu/msm/kgsl_pwrctrl.c +31 −0 Original line number Diff line number Diff line Loading @@ -346,6 +346,8 @@ void kgsl_pwrctrl_pwrlevel_change(struct kgsl_device *device, if (new_level == old_level) return; kgsl_pwrscale_update_stats(device); /* * Set the active and previous powerlevel first in case the clocks are * off - if we don't do this then the pwrlevel change won't take effect Loading Loading @@ -915,6 +917,31 @@ static ssize_t kgsl_pwrctrl_gpu_available_frequencies_show( return num_chars; } static ssize_t kgsl_pwrctrl_gpu_clock_stats_show( struct device *dev, struct device_attribute *attr, char *buf) { struct kgsl_device *device = kgsl_device_from_dev(dev); struct kgsl_pwrctrl *pwr; int index, num_chars = 0; if (device == NULL) return 0; pwr = &device->pwrctrl; mutex_lock(&device->mutex); kgsl_pwrscale_update_stats(device); mutex_unlock(&device->mutex); for (index = 0; index < pwr->num_pwrlevels - 1; index++) num_chars += snprintf(buf + num_chars, PAGE_SIZE - num_chars, "%llu ", pwr->clock_times[index]); if (num_chars < PAGE_SIZE) buf[num_chars++] = '\n'; return num_chars; } static ssize_t kgsl_pwrctrl_reset_count_show(struct device *dev, struct device_attribute *attr, char *buf) Loading Loading @@ -1167,6 +1194,9 @@ static DEVICE_ATTR(gpubusy, 0444, kgsl_pwrctrl_gpubusy_show, static DEVICE_ATTR(gpu_available_frequencies, 0444, kgsl_pwrctrl_gpu_available_frequencies_show, NULL); static DEVICE_ATTR(gpu_clock_stats, 0444, kgsl_pwrctrl_gpu_clock_stats_show, NULL); static DEVICE_ATTR(max_pwrlevel, 0644, kgsl_pwrctrl_max_pwrlevel_show, kgsl_pwrctrl_max_pwrlevel_store); Loading Loading @@ -1212,6 +1242,7 @@ static const struct device_attribute *pwrctrl_attr_list[] = { &dev_attr_deep_nap_timer, &dev_attr_gpubusy, &dev_attr_gpu_available_frequencies, &dev_attr_gpu_clock_stats, &dev_attr_max_pwrlevel, &dev_attr_min_pwrlevel, &dev_attr_thermal_pwrlevel, Loading drivers/gpu/msm/kgsl_pwrctrl.h +2 −0 Original line number Diff line number Diff line Loading @@ -120,6 +120,7 @@ struct kgsl_regulator { * @min_pwrlevel - minimum allowable powerlevel per the user * @num_pwrlevels - number of available power levels * @interval_timeout - timeout in jiffies to be idle before a power event * @clock_times - Each GPU frequency's accumulated active time in us * @strtstp_sleepwake - true if the device supports low latency GPU start/stop * @regulators - array of pointers to kgsl_regulator structs * @pcl - bus scale identifier Loading Loading @@ -172,6 +173,7 @@ struct kgsl_pwrctrl { unsigned int min_pwrlevel; unsigned int num_pwrlevels; unsigned long interval_timeout; u64 clock_times[KGSL_MAX_PWRLEVELS]; bool strtstp_sleepwake; struct kgsl_regulator regulators[KGSL_MAX_REGULATORS]; uint32_t pcl; Loading drivers/gpu/msm/kgsl_pwrscale.c +3 −0 Original line number Diff line number Diff line Loading @@ -127,6 +127,7 @@ EXPORT_SYMBOL(kgsl_pwrscale_busy); */ void kgsl_pwrscale_update_stats(struct kgsl_device *device) { struct kgsl_pwrctrl *pwrctrl = &device->pwrctrl; struct kgsl_pwrscale *psc = &device->pwrscale; BUG_ON(!mutex_is_locked(&device->mutex)); Loading @@ -150,6 +151,8 @@ void kgsl_pwrscale_update_stats(struct kgsl_device *device) device->pwrscale.accum_stats.busy_time += stats.busy_time; device->pwrscale.accum_stats.ram_time += stats.ram_time; device->pwrscale.accum_stats.ram_wait += stats.ram_wait; pwrctrl->clock_times[pwrctrl->active_pwrlevel] += stats.busy_time; } } EXPORT_SYMBOL(kgsl_pwrscale_update_stats); Loading Loading
drivers/gpu/msm/adreno.c +2 −0 Original line number Diff line number Diff line Loading @@ -1544,6 +1544,8 @@ static int adreno_stop(struct kgsl_device *device) adreno_ringbuffer_stop(adreno_dev); kgsl_pwrscale_update_stats(device); adreno_irqctrl(adreno_dev, 0); adreno_ocmem_free(adreno_dev); Loading
drivers/gpu/msm/kgsl_pwrctrl.c +31 −0 Original line number Diff line number Diff line Loading @@ -346,6 +346,8 @@ void kgsl_pwrctrl_pwrlevel_change(struct kgsl_device *device, if (new_level == old_level) return; kgsl_pwrscale_update_stats(device); /* * Set the active and previous powerlevel first in case the clocks are * off - if we don't do this then the pwrlevel change won't take effect Loading Loading @@ -915,6 +917,31 @@ static ssize_t kgsl_pwrctrl_gpu_available_frequencies_show( return num_chars; } static ssize_t kgsl_pwrctrl_gpu_clock_stats_show( struct device *dev, struct device_attribute *attr, char *buf) { struct kgsl_device *device = kgsl_device_from_dev(dev); struct kgsl_pwrctrl *pwr; int index, num_chars = 0; if (device == NULL) return 0; pwr = &device->pwrctrl; mutex_lock(&device->mutex); kgsl_pwrscale_update_stats(device); mutex_unlock(&device->mutex); for (index = 0; index < pwr->num_pwrlevels - 1; index++) num_chars += snprintf(buf + num_chars, PAGE_SIZE - num_chars, "%llu ", pwr->clock_times[index]); if (num_chars < PAGE_SIZE) buf[num_chars++] = '\n'; return num_chars; } static ssize_t kgsl_pwrctrl_reset_count_show(struct device *dev, struct device_attribute *attr, char *buf) Loading Loading @@ -1167,6 +1194,9 @@ static DEVICE_ATTR(gpubusy, 0444, kgsl_pwrctrl_gpubusy_show, static DEVICE_ATTR(gpu_available_frequencies, 0444, kgsl_pwrctrl_gpu_available_frequencies_show, NULL); static DEVICE_ATTR(gpu_clock_stats, 0444, kgsl_pwrctrl_gpu_clock_stats_show, NULL); static DEVICE_ATTR(max_pwrlevel, 0644, kgsl_pwrctrl_max_pwrlevel_show, kgsl_pwrctrl_max_pwrlevel_store); Loading Loading @@ -1212,6 +1242,7 @@ static const struct device_attribute *pwrctrl_attr_list[] = { &dev_attr_deep_nap_timer, &dev_attr_gpubusy, &dev_attr_gpu_available_frequencies, &dev_attr_gpu_clock_stats, &dev_attr_max_pwrlevel, &dev_attr_min_pwrlevel, &dev_attr_thermal_pwrlevel, Loading
drivers/gpu/msm/kgsl_pwrctrl.h +2 −0 Original line number Diff line number Diff line Loading @@ -120,6 +120,7 @@ struct kgsl_regulator { * @min_pwrlevel - minimum allowable powerlevel per the user * @num_pwrlevels - number of available power levels * @interval_timeout - timeout in jiffies to be idle before a power event * @clock_times - Each GPU frequency's accumulated active time in us * @strtstp_sleepwake - true if the device supports low latency GPU start/stop * @regulators - array of pointers to kgsl_regulator structs * @pcl - bus scale identifier Loading Loading @@ -172,6 +173,7 @@ struct kgsl_pwrctrl { unsigned int min_pwrlevel; unsigned int num_pwrlevels; unsigned long interval_timeout; u64 clock_times[KGSL_MAX_PWRLEVELS]; bool strtstp_sleepwake; struct kgsl_regulator regulators[KGSL_MAX_REGULATORS]; uint32_t pcl; Loading
drivers/gpu/msm/kgsl_pwrscale.c +3 −0 Original line number Diff line number Diff line Loading @@ -127,6 +127,7 @@ EXPORT_SYMBOL(kgsl_pwrscale_busy); */ void kgsl_pwrscale_update_stats(struct kgsl_device *device) { struct kgsl_pwrctrl *pwrctrl = &device->pwrctrl; struct kgsl_pwrscale *psc = &device->pwrscale; BUG_ON(!mutex_is_locked(&device->mutex)); Loading @@ -150,6 +151,8 @@ void kgsl_pwrscale_update_stats(struct kgsl_device *device) device->pwrscale.accum_stats.busy_time += stats.busy_time; device->pwrscale.accum_stats.ram_time += stats.ram_time; device->pwrscale.accum_stats.ram_wait += stats.ram_wait; pwrctrl->clock_times[pwrctrl->active_pwrlevel] += stats.busy_time; } } EXPORT_SYMBOL(kgsl_pwrscale_update_stats); Loading