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Commit e0bb3964 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'tc2-pm' of git://git.linaro.org/people/pawelmoll/linux into next/soc 

From Pawel Moll and Nicolas Pitre:
- Fixes to the existing Vexpress DCSCB backend.

- Lorenzo's minimal SPC driver required by the TC2 MCPM backend.

- The MCPM backend enabling SMP secondary boot and CPU hotplug
  on the VExpress TC2 big.LITTLE platform.

- MCPM suspend method to the TC2 backend allowing basic CPU
  idle/suspend.  The cpuidle driver that hooks into this will be
  submitted separately.

* tag 'tc2-pm' of git://git.linaro.org/people/pawelmoll/linux

:
  ARM: vexpress/TC2: implement PM suspend method
  ARM: vexpress/TC2: basic PM support
  ARM: vexpress: Add SCC to V2P-CA15_A7's device tree
  ARM: vexpress/TC2: add Serial Power Controller (SPC) support
  ARM: vexpress/dcscb: fix cache disabling sequences

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 3b2f64d0 e607b0f9

Documentation/devicetree/bindings/arm/vexpress-scc.txt

0 → 100644
+33 −0
Original line number Diff line number Diff line 
ARM Versatile Express Serial Configuration Controller

-----------------------------------------------------



Test chips for ARM Versatile Express platform implement SCC (Serial

Configuration Controller) interface, used to set initial conditions

for the test chip.



In some cases its registers are also mapped in normal address space

and can be used to obtain runtime information about the chip internals

(like silicon temperature sensors) and as interface to other subsystems

like platform configuration control and power management.



Required properties:



- compatible value: "arm,vexpress-scc,<model>", "arm,vexpress-scc";

		    where <model> is the full tile model name (as used

		    in the tile's Technical Reference Manual),

		    eg. for Coretile Express A15x2 A7x3 (V2P-CA15_A7):

	compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";



Optional properties:



- reg: when the SCC is memory mapped, physical address and size of the

       registers window

- interrupts: when the SCC can generate a system-level interrupt



Example:



	scc@7fff0000 {

		compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";

		reg = <0 0x7fff0000 0 0x1000>;

		interrupts = <0 95 4>;

	};

arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts

+6 −0
Original line number Diff line number Diff line
@@ -125,6 +125,12 @@ 
		clock-names = "apb_pclk";

	};



        scc@7fff0000 {

		compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";

		reg = <0 0x7fff0000 0 0x1000>;

		interrupts = <0 95 4>;

        };



	timer {

		compatible = "arm,armv7-timer";

		interrupts = <1 13 0xf08>,

arch/arm/mach-vexpress/Kconfig

+8 −0
Original line number Diff line number Diff line
@@ -66,4 +66,12 @@ config ARCH_VEXPRESS_DCSCB 
	  This is needed to provide CPU and cluster power management

	  on RTSM implementing big.LITTLE.



config ARCH_VEXPRESS_TC2_PM

	bool "Versatile Express TC2 power management"

	depends on MCPM

	select ARM_CCI

	help

	  Support for CPU and cluster power management on Versatile Express

	  with a TC2 (A15x2 A7x3) big.LITTLE core tile.



endmenu

arch/arm/mach-vexpress/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -7,5 +7,6 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \ 
obj-y					:= v2m.o

obj-$(CONFIG_ARCH_VEXPRESS_CA9X4)	+= ct-ca9x4.o

obj-$(CONFIG_ARCH_VEXPRESS_DCSCB)	+= dcscb.o	dcscb_setup.o

obj-$(CONFIG_ARCH_VEXPRESS_TC2_PM)	+= tc2_pm.o spc.o

obj-$(CONFIG_SMP)			+= platsmp.o

obj-$(CONFIG_HOTPLUG_CPU)		+= hotplug.o

arch/arm/mach-vexpress/dcscb.c

+37 −21
Original line number Diff line number Diff line
@@ -136,14 +136,29 @@ static void dcscb_power_down(void) 
		/*

		 * Flush all cache levels for this cluster.

		 *

		 * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need

		 * a preliminary flush here for those CPUs.  At least, that's

		 * the theory -- without the extra flush, Linux explodes on

		 * RTSM (to be investigated).

		 * To do so we do:

		 * - Clear the SCTLR.C bit to prevent further cache allocations

		 * - Flush the whole cache

		 * - Clear the ACTLR "SMP" bit to disable local coherency

		 *

		 * Let's do it in the safest possible way i.e. with

		 * no memory access within the following sequence

		 * including to the stack.

		 */

		flush_cache_all();

		set_cr(get_cr() & ~CR_C);

		flush_cache_all();

		asm volatile(

		"mrc	p15, 0, r0, c1, c0, 0	@ get CR \n\t"

		"bic	r0, r0, #"__stringify(CR_C)" \n\t"

		"mcr	p15, 0, r0, c1, c0, 0	@ set CR \n\t"

		"isb	\n\t"

		"bl	v7_flush_dcache_all \n\t"

		"clrex	\n\t"

		"mrc	p15, 0, r0, c1, c0, 1	@ get AUXCR \n\t"

		"bic	r0, r0, #(1 << 6)	@ disable local coherency \n\t"

		"mcr	p15, 0, r0, c1, c0, 1	@ set AUXCR \n\t"

		"isb	\n\t"

		"dsb	"

		: : : "r0","r1","r2","r3","r4","r5","r6","r7",

		      "r9","r10","r11","lr","memory");



		/*

		 * This is a harmless no-op.  On platforms with a real
@@ -152,9 +167,6 @@ static void dcscb_power_down(void) 
		 */

		outer_flush_all();



		/* Disable local coherency by clearing the ACTLR "SMP" bit: */

		set_auxcr(get_auxcr() & ~(1 << 6));



		/*

		 * Disable cluster-level coherency by masking

		 * incoming snoops and DVM messages:
@@ -167,18 +179,22 @@ static void dcscb_power_down(void) 


		/*

		 * Flush the local CPU cache.

		 *

		 * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need

		 * a preliminary flush here for those CPUs.  At least, that's

		 * the theory -- without the extra flush, Linux explodes on

		 * RTSM (to be investigated).

		 * Let's do it in the safest possible way as above.

		 */

		flush_cache_louis();

		set_cr(get_cr() & ~CR_C);

		flush_cache_louis();



		/* Disable local coherency by clearing the ACTLR "SMP" bit: */

		set_auxcr(get_auxcr() & ~(1 << 6));

		asm volatile(

		"mrc	p15, 0, r0, c1, c0, 0	@ get CR \n\t"

		"bic	r0, r0, #"__stringify(CR_C)" \n\t"

		"mcr	p15, 0, r0, c1, c0, 0	@ set CR \n\t"

		"isb	\n\t"

		"bl	v7_flush_dcache_louis \n\t"

		"clrex	\n\t"

		"mrc	p15, 0, r0, c1, c0, 1	@ get AUXCR \n\t"

		"bic	r0, r0, #(1 << 6)	@ disable local coherency \n\t"

		"mcr	p15, 0, r0, c1, c0, 1	@ set AUXCR \n\t"

		"isb	\n\t"

		"dsb	"

		: : : "r0","r1","r2","r3","r4","r5","r6","r7",

		      "r9","r10","r11","lr","memory");

	}



	__mcpm_cpu_down(cpu, cluster);