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Commit e086df92 authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'sunxi-core-for-3.13' of https://github.com/mripard/linux into next/soc 

From Maxime Ripard:
Allwinner sunXi SoCs machine additions for 3.13

Nothing outstanding here, mostly some documentation cleanup, and the split of
the previous generic machine declaration into three different machines to
handle the sun4i/sun5i, sun6i and sun7i separately.

* tag 'sunxi-core-for-3.13' of https://github.com/mripard/linux

:
  Documentation: dt: Remove clock gates IDs list for Allwinner SoCs
  Documentation: dt: Remove interrupt sources list for Allwinner SoCs
  Documentation: sunxi: Update Allwinner SoC documentation
  Documentation: sunxi: Update A13 user manual dead link
  ARM: sunxi: Order Kconfig options alphabetically
  ARM: sunxi: Simplify restart setup code
  ARM: sunxi: Split out the DT machines for sun6i and sun7i

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 0fc869e8 fc42ef51

Documentation/arm/sunxi/README

+25 −1
Original line number Diff line number Diff line
@@ -10,6 +10,10 @@ SunXi family 
  Linux kernel mach directory: arch/arm/mach-sunxi



  Flavors:

    * ARM926 based SoCs

      - Allwinner F20 (sun3i)

        + Not Supported



    * ARM Cortex-A8 based SoCs

      - Allwinner A10 (sun4i)

        + Datasheet
@@ -25,4 +29,24 @@ SunXi family 
        + Datasheet

	  http://dl.linux-sunxi.org/A13/A13%20Datasheet%20-%20v1.12%20%282012-03-29%29.pdf

        + User Manual

	  http://dl.linux-sunxi.org/A13/A13%20User%20Manual%20-%20v1.2%20%282013-08-08%29.pdf
 
          http://dl.linux-sunxi.org/A13/A13%20User%20Manual%20-%20v1.2%20%282013-01-08%29.pdf



    * Dual ARM Cortex-A7 based SoCs

      - Allwinner A20 (sun7i)

        + User Manual

          http://dl.linux-sunxi.org/A20/A20%20User%20Manual%202013-03-22.pdf



      - Allwinner A23

        + Not Supported



    * Quad ARM Cortex-A7 based SoCs

      - Allwinner A31 (sun6i)

        + Datasheet

          http://dl.linux-sunxi.org/A31/A31%20Datasheet%20-%20v1.00%20(2012-12-24).pdf



      - Allwinner A31s (sun6i)

        + Not Supported



    * Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs

      - Allwinner A80

        + Not Supported
 
 No newline at end of file

Documentation/devicetree/bindings/clock/sunxi.txt

+2 −2
Original line number Diff line number Diff line
@@ -45,8 +45,8 @@ Additionally, "allwinner,*-gates-clk" clocks require: 


Clock consumers should specify the desired clocks they use with a

"clocks" phandle cell. Consumers that are using a gated clock should

provide an additional ID in their clock property. The values of this

ID are documented in sunxi/<soc>-gates.txt.

provide an additional ID in their clock property. This ID is the

offset of the bit controlling this particular gate in the register.



For example:

Documentation/devicetree/bindings/clock/sunxi/sun4i-a10-gates.txt

deleted100644 → 0
+0 −93
Original line number Diff line number Diff line 
Gate clock outputs

------------------



  * AXI gates ("allwinner,sun4i-axi-gates-clk")



    DRAM					0



  * AHB gates ("allwinner,sun4i-ahb-gates-clk")



    USB0					0

    EHCI0					1

    OHCI0					2*

    EHCI1					3

    OHCI1					4*

    SS						5

    DMA						6

    BIST					7

    MMC0					8

    MMC1					9

    MMC2					10

    MMC3					11

    MS						12**

    NAND					13

    SDRAM					14



    ACE						16

    EMAC					17

    TS						18



    SPI0					20

    SPI1					21

    SPI2					22

    SPI3					23

    PATA					24

    SATA					25**

    GPS						26*



    VE						32

    TVD						33

    TVE0					34

    TVE1					35

    LCD0					36

    LCD1					37



    CSI0					40

    CSI1					41



    HDMI					43

    DE_BE0					44

    DE_BE1					45

    DE_FE1					46

    DE_FE1					47



    MP						50



    MALI400					52



  * APB0 gates ("allwinner,sun4i-apb0-gates-clk")



    CODEC					0

    SPDIF					1*

    AC97					2

    IIS						3



    PIO						5

    IR0						6

    IR1						7



    KEYPAD					10



  * APB1 gates ("allwinner,sun4i-apb1-gates-clk")



    I2C0					0

    I2C1					1

    I2C2					2



    CAN						4

    SCR						5

    PS20					6

    PS21					7



    UART0					16

    UART1					17

    UART2					18

    UART3					19

    UART4					20

    UART5					21

    UART6					22

    UART7					23



Notation:

 [*]:  The datasheet didn't mention these, but they are present on AW code

 [**]: The datasheet had this marked as "NC" but they are used on AW code

Documentation/devicetree/bindings/clock/sunxi/sun5i-a10s-gates.txt

deleted100644 → 0
+0 −75
Original line number Diff line number Diff line 
Gate clock outputs

------------------



  * AXI gates ("allwinner,sun4i-axi-gates-clk")



    DRAM					0



  * AHB gates ("allwinner,sun5i-a10s-ahb-gates-clk")



    USB0					0

    EHCI0					1

    OHCI0					2



    SS						5

    DMA						6

    BIST					7

    MMC0					8

    MMC1					9

    MMC2					10



    NAND					13

    SDRAM					14



    EMAC					17

    TS						18



    SPI0					20

    SPI1					21

    SPI2					22



    GPS						26



    HSTIMER					28



    VE						32



    TVE						34



    LCD						36



    CSI						40



    HDMI					43

    DE_BE					44



    DE_FE					46



    IEP						51

    MALI400					52



  * APB0 gates ("allwinner,sun5i-a10s-apb0-gates-clk")



    CODEC					0



    IIS						3



    PIO						5

    IR						6



    KEYPAD					10



  * APB1 gates ("allwinner,sun5i-a10s-apb1-gates-clk")



    I2C0					0

    I2C1					1

    I2C2					2



    UART0					16

    UART1					17

    UART2					18

    UART3					19



Notation:

 [*]:  The datasheet didn't mention these, but they are present on AW code

 [**]: The datasheet had this marked as "NC" but they are used on AW code

Documentation/devicetree/bindings/clock/sunxi/sun5i-a13-gates.txt

deleted100644 → 0
+0 −58
Original line number Diff line number Diff line 
Gate clock outputs

------------------



  * AXI gates ("allwinner,sun4i-axi-gates-clk")



    DRAM					0



  * AHB gates ("allwinner,sun5i-a13-ahb-gates-clk")



    USBOTG					0

    EHCI					1

    OHCI					2



    SS						5

    DMA						6

    BIST					7

    MMC0					8

    MMC1					9

    MMC2					10



    NAND					13

    SDRAM					14



    SPI0					20

    SPI1					21

    SPI2					22



    STIMER					28



    VE						32



    LCD						36



    CSI						40



    DE_BE					44



    DE_FE					46



    IEP						51

    MALI400					52



  * APB0 gates ("allwinner,sun5i-a13-apb0-gates-clk")



    CODEC					0



    PIO						5

    IR						6



  * APB1 gates ("allwinner,sun5i-a13-apb1-gates-clk")



    I2C0					0

    I2C1					1

    I2C2					2



    UART1					17



    UART3					19