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Commit e078c823 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "msm: ipa3: update IPA 3.0 registers"

parents 9481f8f8 798645ea

drivers/platform/msm/ipa/ipa_v3/ipa.c

+5 −5
Original line number Diff line number Diff line
@@ -1494,11 +1494,11 @@ static void ipa_q6_disable_agg_reg(struct ipa_register_write *reg_write, 


	reg_write->offset = IPA_ENDP_INIT_AGGR_N_OFST_v3_0(ep_idx);

	reg_write->value =

		(1 & IPA_ENDP_INIT_AGGR_n_AGGR_FORCE_CLOSE_BMSK) <<

		IPA_ENDP_INIT_AGGR_n_AGGR_FORCE_CLOSE_SHFT;

		(1 & IPA_ENDP_INIT_AGGR_N_AGGR_FORCE_CLOSE_BMSK) <<

		IPA_ENDP_INIT_AGGR_N_AGGR_FORCE_CLOSE_SHFT;

	reg_write->value_mask =

		IPA_ENDP_INIT_AGGR_n_AGGR_FORCE_CLOSE_BMSK <<

		IPA_ENDP_INIT_AGGR_n_AGGR_FORCE_CLOSE_SHFT;

		IPA_ENDP_INIT_AGGR_N_AGGR_FORCE_CLOSE_BMSK <<

		IPA_ENDP_INIT_AGGR_N_AGGR_FORCE_CLOSE_SHFT;



	reg_write->value |=

		((0 & IPA_ENDP_INIT_AGGR_N_AGGR_EN_BMSK) <<
@@ -1684,7 +1684,7 @@ int _ipa_init_sram_v3_0(void) 


	phys_addr = ipa_ctx->ipa_wrapper_base +

		ipa_ctx->ctrl->ipa_reg_base_ofst +

		IPA_SRAM_SW_FIRST_v3_0;

		IPA_SRAM_DIRECT_ACCESS_N_OFST_v3_0(0);



	ipa_sram_mmio = ioremap(phys_addr,

		ipa_ctx->smem_sz - ipa_ctx->smem_restricted_bytes);

drivers/platform/msm/ipa/ipa_v3/ipa_i.h

+0 −1
Original line number Diff line number Diff line
@@ -1404,7 +1404,6 @@ u8 *ipa_pad_to_32(u8 *dest); 
int ipa_init_hw(void);

struct ipa_rt_tbl *__ipa_find_rt_tbl(enum ipa_ip_type ip, const char *name);

int ipa_set_single_ndp_per_mbim(bool);

int ipa_set_hw_timer_fix_for_mbim_aggr(bool);

void ipa_debugfs_init(void);

void ipa_debugfs_remove(void);

drivers/platform/msm/ipa/ipa_v3/ipa_nat.c

+2 −1
Original line number Diff line number Diff line
@@ -90,7 +90,8 @@ static int ipa_nat_mmap(struct file *filp, struct vm_area_struct *vma) 
		}

		phys_addr = ipa_ctx->ipa_wrapper_base +

			ipa_ctx->ctrl->ipa_reg_base_ofst +

			IPA_SRAM_DIRECT_ACCESS_N_OFST(IPA_NAT_PHYS_MEM_OFFSET);

			IPA_SRAM_DIRECT_ACCESS_N_OFST_v3_0(

				IPA_NAT_PHYS_MEM_OFFSET);



		if (remap_pfn_range(

			 vma, vma->vm_start,

drivers/platform/msm/ipa/ipa_v3/ipa_reg.h

+43 −120
Original line number Diff line number Diff line
@@ -13,111 +13,40 @@ 
#ifndef __IPA_REG_H__

#define __IPA_REG_H__



/*

 * IPA's BAM specific registers

 * Used for IPA HW 1.0 only

 */



#define IPA_BAM_REG_BASE_OFST 0x00004000

#define IPA_BAM_CNFG_BITS_OFST 0x7c

#define IPA_BAM_REMAP_SIZE (0x1000)



#define IPA_FILTER_FILTER_EN_BMSK 0x1

#define IPA_FILTER_FILTER_EN_SHFT 0x0

#define IPA_AGGREGATION_SPARE_REG_2_OFST 0x00002094

#define IPA_AGGREGATION_QCNCM_SIG0_SHFT 16

#define IPA_AGGREGATION_QCNCM_SIG1_SHFT 8



#define IPA_AGGREGATION_SPARE_REG_1_OFST 0x00002090

#define IPA_AGGREGATION_SPARE_REG_2_OFST 0x00002094



#define IPA_AGGREGATION_SINGLE_NDP_MSK 0x1

#define IPA_AGGREGATION_SINGLE_NDP_BMSK 0xfffffffe



#define IPA_AGGREGATION_MODE_MSK 0x1

#define IPA_AGGREGATION_MODE_SHFT 31

#define IPA_AGGREGATION_MODE_BMSK 0x7fffffff



#define IPA_AGGREGATION_QCNCM_SIG_BMSK 0xff000000



#define IPA_FILTER_FILTER_EN_BMSK 0x1

#define IPA_FILTER_FILTER_EN_SHFT 0x0



#define IPA_AGGREGATION_HW_TIMER_FIX_MBIM_AGGR_SHFT 2

#define IPA_AGGREGATION_HW_TIMER_FIX_MBIM_AGGR_BMSK 0x4



#define IPA_HEAD_OF_LINE_BLOCK_EN_OFST 0x00000044



/*

 * End of IPA 1.0 Registers

 */



#define IPA_IRQ_STTS_EE_n_ADDR(n) (0x00003008 + 0x1000 * (n))



/*

 * IPA HW 2.0 Registers

 */

#define IPA_REG_BASE 0x0



#define IPA_IRQ_STTS_EE_n_ADDR(n) (IPA_REG_BASE + 0x00001008 + 0x1000 * (n))

#define IPA_IRQ_STTS_EE_n_MAXn 3



#define IPA_IRQ_EN_EE_n_ADDR(n) (IPA_REG_BASE + 0x0000100c + 0x1000 * (n))

#define IPA_IRQ_EN_EE_n_MAXn 3

#define IPA_IRQ_EN_EE_n_ADDR(n) (0x0000300c + 0x1000 * (n))



#define IPA_IRQ_CLR_EE_n_ADDR(n) (0x00003010 + 0x1000 * (n))



#define IPA_IRQ_CLR_EE_n_ADDR(n) (IPA_REG_BASE + 0x00001010 + 0x1000 * (n))

#define IPA_IRQ_CLR_EE_n_MAXn 3



#define IPA_IRQ_SUSPEND_INFO_EE_n_ADDR(n) \

				(IPA_REG_BASE + 0x00001098 + 0x1000 * (n))

#define IPA_IRQ_SUSPEND_INFO_EE_n_MAXn 3

/*

 * End of IPA 2.0 Registers

 */

#define IPA_IRQ_SUSPEND_INFO_EE_n_ADDR(n) (0x00003098 + 0x1000 * (n))



/*

 * IPA HW 2.5 Registers

 */

#define IPA_BCR_OFST 0x000005B0

#define IPA_COUNTER_CFG_OFST 0x000005E8

#define IPA_BCR_OFST 0x000001D0

#define IPA_COUNTER_CFG_OFST 0x000001f0

#define IPA_COUNTER_CFG_EOT_COAL_GRAN_BMSK 0xF

#define IPA_COUNTER_CFG_EOT_COAL_GRAN_SHFT 0x0

#define IPA_COUNTER_CFG_AGGR_GRAN_BMSK 0x1F0

#define IPA_COUNTER_CFG_AGGR_GRAN_SHFT 0x4

 /*

 * End of IPA 2.5 Registers

 */



/*

 * IPA HW 2.6/2.6L Registers

 */

#define IPA_ENABLED_PIPES_OFST 0x000005DC

/*

 * End of IPA 2.6/2.6L Registers

 */

#define IPA_ENABLED_PIPES_OFST 0x00000038



/*

Common Registers

*/

#define IPA_REG_BASE_OFST_v3_0 0x00040000

#define IPA_COMP_SW_RESET_OFST 0x0000003c

#define IPA_COMP_SW_RESET_OFST 0x00000040



#define IPA_VERSION_OFST 0x00000034

#define IPA_COMP_HW_VERSION_OFST 0x00000030



#define IPA_SHARED_MEM_SIZE_OFST_v3_0 0x00000050

#define IPA_SHARED_MEM_SIZE_OFST_v3_0 0x00000054

#define IPA_SHARED_MEM_SIZE_SHARED_MEM_BADDR_BMSK_v3_0 0xffff0000

#define IPA_SHARED_MEM_SIZE_SHARED_MEM_BADDR_SHFT_v3_0 0x10

#define IPA_SHARED_MEM_SIZE_SHARED_MEM_SIZE_BMSK_v3_0  0xffff

#define IPA_SHARED_MEM_SIZE_SHARED_MEM_SIZE_SHFT_v3_0  0x0



#define IPA_ENDP_INIT_AGGR_N_OFST_v3_0(n) (0x00000320 + 0x4 * (n))



#define IPA_ENDP_INIT_ROUTE_N_OFST_v3_0(n) (0x00000370 + 0x4 * (n))

#define IPA_ENDP_INIT_ROUTE_N_OFST_v3_0(n) (0x00000828 + 0x60 * (n))

#define IPA_ENDP_INIT_ROUTE_N_ROUTE_TABLE_INDEX_BMSK 0x1f

#define IPA_ENDP_INIT_ROUTE_N_ROUTE_TABLE_INDEX_SHFT 0x0



#define IPA_ROUTE_OFST_v3_0 0x00000044

#define IPA_ROUTE_OFST_v3_0 0x00000048



#define IPA_ROUTE_ROUTE_DIS_SHFT 0x0

#define IPA_ROUTE_ROUTE_DIS_BMSK 0x1
@@ -129,19 +58,23 @@ Common Registers 
#define IPA_ROUTE_ROUTE_FRAG_DEF_PIPE_BMSK 0x3e0000

#define IPA_ROUTE_ROUTE_FRAG_DEF_PIPE_SHFT 0x11



#define IPA_FILTER_OFST_v3_0 0x00000048

#define IPA_FILTER_OFST_v3_0 0x0000004c

#define IPA_FILTER_FILTER_EN_BMSK 0x1

#define IPA_FILTER_FILTER_EN_SHFT 0x0



#define IPA_SRAM_DIRECT_ACCESS_N_OFST_v3_0(n) (0x00005000 + 0x4 * (n))

#define IPA_SRAM_DIRECT_ACCESS_N_OFST(n) (0x00004000 + 0x4 * (n))

#define IPA_SRAM_SW_FIRST_v3_0 0x00005000

#define IPA_SRAM_DIRECT_ACCESS_N_OFST_v3_0(n) (0x00007000 + 0x4 * (n))

#define IPA_ROUTE_ROUTE_DEF_HDR_TABLE_BMSK 0x40

#define IPA_ENDP_INIT_NAT_N_NAT_EN_SHFT 0x0

#define IPA_COMP_CFG_OFST 0x00000038

#define IPA_COMP_CFG_OFST 0x0000003C



#define IPA_AGGR_FORCE_CLOSE_OFST 0x000005a0

#define IPA_AGGR_FORCE_CLOSE_OFST_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK 0xFFFFF

#define IPA_AGGR_FORCE_CLOSE_OFST_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT 0



#define IPA_ENDP_INIT_AGGR_n_AGGR_FORCE_CLOSE_BMSK 0x1

#define IPA_ENDP_INIT_AGGR_n_AGGR_FORCE_CLOSE_SHFT 0x16

#define IPA_ENDP_INIT_AGGR_n_AGGR_PKT_LIMIT_BMSK 0x1f8000

#define IPA_ENDP_INIT_AGGR_n_AGGR_PKT_LIMIT_SHFT 0xf

#define IPA_ENDP_INIT_AGGR_N_OFST_v3_0(n) (0x00000824 + 0x60 * (n))

#define IPA_ENDP_INIT_AGGR_N_AGGR_FORCE_CLOSE_BMSK 0x1

#define IPA_ENDP_INIT_AGGR_N_AGGR_FORCE_CLOSE_SHFT 0x16

#define IPA_ENDP_INIT_AGGR_N_AGGR_PKT_LIMIT_BMSK 0x1f8000

#define IPA_ENDP_INIT_AGGR_N_AGGR_PKT_LIMIT_SHFT 0xf

#define IPA_ENDP_INIT_AGGR_N_AGGR_TIME_LIMIT_BMSK 0x7c00

#define IPA_ENDP_INIT_AGGR_N_AGGR_TIME_LIMIT_SHFT 0xa

#define IPA_ENDP_INIT_AGGR_N_AGGR_BYTE_LIMIT_BMSK 0x3e0
@@ -151,7 +84,7 @@ Common Registers 
#define IPA_ENDP_INIT_AGGR_N_AGGR_EN_BMSK 0x3

#define IPA_ENDP_INIT_AGGR_N_AGGR_EN_SHFT 0x0



#define IPA_ENDP_INIT_MODE_N_OFST_v3_0(n) (0x000002c0 + 0x4 * (n))

#define IPA_ENDP_INIT_MODE_N_OFST_v3_0(n) (0x00000820 + 0x60 * (n))

#define IPA_ENDP_INIT_MODE_N_RMSK 0x7f

#define IPA_ENDP_INIT_MODE_N_MAX 19

#define IPA_ENDP_INIT_MODE_N_DEST_PIPE_INDEX_BMSK_v3_0 0x1f0
@@ -159,7 +92,7 @@ Common Registers 
#define IPA_ENDP_INIT_MODE_N_MODE_BMSK 0x7

#define IPA_ENDP_INIT_MODE_N_MODE_SHFT 0x0



#define IPA_ENDP_INIT_HDR_N_OFST_v3_0(n) (0x00000170 + 0x4 * (n))

#define IPA_ENDP_INIT_HDR_N_OFST_v3_0(n) (0x00000810 + 0x60 * (n))

#define IPA_ENDP_INIT_HDR_N_HDR_LEN_BMSK 0x3f

#define IPA_ENDP_INIT_HDR_N_HDR_LEN_SHFT 0x0

#define IPA_ENDP_INIT_HDR_N_HDR_ADDITIONAL_CONST_LEN_BMSK 0x7e000
@@ -179,12 +112,11 @@ Common Registers 
#define IPA_ENDP_INIT_HDR_N_HDR_OFST_METADATA_SHFT 0x7

#define IPA_ENDP_INIT_HDR_N_HDR_OFST_METADATA_BMSK 0x1f80



#define IPA_ENDP_INIT_NAT_N_OFST_v3_0(n) (0x00000120 + 0x4 * (n))

#define IPA_ENDP_INIT_NAT_N_OFST_v3_0(n) (0x0000080C + 0x60 * (n))

#define IPA_ENDP_INIT_NAT_N_NAT_EN_BMSK 0x3

#define IPA_ENDP_INIT_NAT_N_NAT_EN_SHFT 0x0





#define IPA_ENDP_INIT_HDR_EXT_n_OFST_v3_0(n) (0x000001c0 + 0x4 * (n))

#define IPA_ENDP_INIT_HDR_EXT_n_OFST_v3_0(n) (0x00000814 + 0x60 * (n))

#define IPA_ENDP_INIT_HDR_EXT_n_HDR_ENDIANNESS_BMSK 0x1

#define IPA_ENDP_INIT_HDR_EXT_n_HDR_ENDIANNESS_SHFT 0x0

#define IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_VALID_BMSK 0x2
@@ -198,37 +130,32 @@ Common Registers 
#define IPA_ENDP_INIT_HDR_EXT_n_HDR_PAD_TO_ALIGNMENT_SHFT 0xa

#define IPA_ENDP_INIT_HDR_EXT_n_HDR_PAD_TO_ALIGNMENT_BMSK_v3_0 0x3c00



#define IPA_SINGLE_NDP_MODE_OFST 0x00000068

#define IPA_QCNCM_OFST 0x00000064



#define IPA_FILTER_FILTER_DIS_BMSK 0x1

#define IPA_FILTER_FILTER_DIS_SHFT 0x0

#define IPA_SINGLE_NDP_MODE_OFST 0x00000064

#define IPA_QCNCM_OFST 0x00000060



#define IPA_ENDP_INIT_CTRL_N_OFST(n) (0x00000070 + 0x4 * (n))

#define IPA_ENDP_INIT_CTRL_N_RMSK 0x1

#define IPA_ENDP_INIT_CTRL_N_MAX 19

#define IPA_ENDP_INIT_CTRL_N_OFST(n) (0x00000700 + 0x60 * (n))

#define IPA_ENDP_INIT_CTRL_N_ENDP_SUSPEND_BMSK 0x1

#define IPA_ENDP_INIT_CTRL_N_ENDP_SUSPEND_SHFT 0x0

#define IPA_ENDP_INIT_CTRL_N_ENDP_DELAY_BMSK 0x2

#define IPA_ENDP_INIT_CTRL_N_ENDP_DELAY_SHFT 0x1



#define IPA_ENDP_INIT_HOL_BLOCK_EN_N_OFST_v3_0(n) (0x000003c0 + 0x4 * (n))

#define IPA_ENDP_INIT_HOL_BLOCK_EN_N_OFST_v3_0(n) (0x0000082c + 0x60 * (n))

#define IPA_ENDP_INIT_HOL_BLOCK_EN_N_RMSK 0x1

#define IPA_ENDP_INIT_HOL_BLOCK_EN_N_MAX 19

#define IPA_ENDP_INIT_HOL_BLOCK_EN_N_EN_BMSK 0x1

#define IPA_ENDP_INIT_HOL_BLOCK_EN_N_EN_SHFT 0x0



#define IPA_ENDP_INIT_DEAGGR_n_OFST_v3_0(n) (0x00000470 + 0x04 * (n))

#define IPA_ENDP_INIT_DEAGGR_n_OFST_v3_0(n) (0x00000834 + 0x60 * (n))

#define IPA_ENDP_INIT_DEAGGR_n_DEAGGR_HDR_LEN_BMSK 0x3F

#define IPA_ENDP_INIT_DEAGGR_n_DEAGGR_HDR_LEN_SHFT 0x0

#define IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_VALID_BMSK 0x40

#define IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_VALID_SHFT 0x6

#define IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_VALID_SHFT 0x7

#define IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_LOCATION_BMSK 0x3F00

#define IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_LOCATION_SHFT 0x8

#define IPA_ENDP_INIT_DEAGGR_n_MAX_PACKET_LEN_BMSK 0xFFFF0000

#define IPA_ENDP_INIT_DEAGGR_n_MAX_PACKET_LEN_SHFT 0x10



#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_N_OFST_v3_0(n) (0x00000420 + 0x4 * (n))

#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_N_OFST_v3_0(n) (0x00000830 + 0x60 * (n))

#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_N_RMSK 0x1ff

#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_N_MAX 19

#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_N_TIMER_BMSK 0x1ff
@@ -254,13 +181,13 @@ Common Registers 
#define IPA_DEBUG_CNT_CTRL_N_DBG_CNT_EN_BMSK 0x1

#define IPA_DEBUG_CNT_CTRL_N_DBG_CNT_EN_SHFT 0x0



#define IPA_ENDP_STATUS_n_OFST(n) (0x000004c0 + 0x4 * (n))

#define IPA_ENDP_STATUS_n_OFST(n) (0x00000840 + 0x60 * (n))

#define IPA_ENDP_STATUS_n_STATUS_ENDP_BMSK 0x3e

#define IPA_ENDP_STATUS_n_STATUS_ENDP_SHFT 0x1

#define IPA_ENDP_STATUS_n_STATUS_EN_BMSK 0x1

#define IPA_ENDP_STATUS_n_STATUS_EN_SHFT 0x0



#define IPA_ENDP_INIT_CFG_n_OFST(n) (0x000000c0 + 0x4 * (n))

#define IPA_ENDP_INIT_CFG_n_OFST(n) (0x00000808 + 0x60 * (n))

#define IPA_ENDP_INIT_CFG_n_RMSK 0x7f

#define IPA_ENDP_INIT_CFG_n_MAXn 19

#define IPA_ENDP_INIT_CFG_n_CS_METADATA_HDR_OFFSET_BMSK 0x78
@@ -270,13 +197,13 @@ Common Registers 
#define IPA_ENDP_INIT_CFG_n_FRAG_OFFLOAD_EN_BMSK 0x1

#define IPA_ENDP_INIT_CFG_n_FRAG_OFFLOAD_EN_SHFT 0x0



#define IPA_ENDP_INIT_HDR_METADATA_MASK_n_OFST(n) (0x00000220 + 0x4 * (n))

#define IPA_ENDP_INIT_HDR_METADATA_MASK_n_OFST(n) (0x00000818 + 0x60 * (n))

#define IPA_ENDP_INIT_HDR_METADATA_MASK_n_RMSK 0xffffffff

#define IPA_ENDP_INIT_HDR_METADATA_MASK_n_MAXn 19

#define IPA_ENDP_INIT_HDR_METADATA_MASK_n_METADATA_MASK_BMSK 0xffffffff

#define IPA_ENDP_INIT_HDR_METADATA_MASK_n_METADATA_MASK_SHFT 0x0



#define IPA_ENDP_INIT_HDR_METADATA_n_OFST(n) (0x00000270 + 0x4 * (n))

#define IPA_ENDP_INIT_HDR_METADATA_n_OFST(n) (0x0000081c + 0x60 * (n))

#define IPA_ENDP_INIT_HDR_METADATA_n_MUX_ID_BMASK 0xFF0000

#define IPA_ENDP_INIT_HDR_METADATA_n_MUX_ID_SHFT 0x10
@@ -298,15 +225,11 @@ Common Registers 
#define IPA_SRC_RSRC_GRP_XY_RSRC_TYPE_n_SRC_RSRC_GRP_X_MIN_LIMIT_BMSK 0xFF

#define IPA_SRC_RSRC_GRP_XY_RSRC_TYPE_n_SRC_RSRC_GRP_X_MIN_LIMIT_SHFT 0



#define IPA_IRQ_EE_UC_n_OFFS(n) (0x0000101c + 0x1000 * (n))

#define IPA_IRQ_EE_UC_n_RMSK 0x1

#define IPA_IRQ_EE_UC_n_MAXn 3

#define IPA_IRQ_EE_UC_n_INT_BMSK 0x1

#define IPA_IRQ_EE_UC_n_INT_SHFT 0x0

#define IPA_IRQ_EE_UC_n_OFFS(n) (0x0000301c + 0x1000 * (n))



#define IPA_UC_MAILBOX_m_n_OFFS_v3_0(m, n) (0x00022000 + 0x80 * (m) + 0x4 * (n))



#define IPA_SYS_PKT_PROC_CNTXT_BASE_OFST (0x000005d8)

#define IPA_LOCAL_PKT_PROC_CNTXT_BASE_OFST (0x000005e0)

#define IPA_SYS_PKT_PROC_CNTXT_BASE_OFST (0x000001e0)

#define IPA_LOCAL_PKT_PROC_CNTXT_BASE_OFST (0x000001e8)



#endif

drivers/platform/msm/ipa/ipa_v3/ipa_uc.c

+2 −1
Original line number Diff line number Diff line
@@ -465,7 +465,8 @@ int ipa_uc_interface_init(void) 
	mutex_init(&ipa_ctx->uc_ctx.uc_lock);



	phys_addr = ipa_ctx->ipa_wrapper_base +

		ipa_ctx->ctrl->ipa_reg_base_ofst + IPA_SRAM_SW_FIRST_v3_0;

		ipa_ctx->ctrl->ipa_reg_base_ofst +

		IPA_SRAM_DIRECT_ACCESS_N_OFST_v3_0(0);

	ipa_ctx->uc_ctx.uc_sram_mmio = ioremap(phys_addr,

					       IPA_RAM_UC_SMEM_SIZE);

	if (!ipa_ctx->uc_ctx.uc_sram_mmio) {