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Commit e0421bbe authored by dmitry pervushin's avatar dmitry pervushin Committed by Russell King
Browse files

[ARM] 5530/1: Freescale STMP: get rid of HW_zzz macros [1/3] 



Replace HW_zzz register access macros by regular __raw_readl/__raw_writel calls

Signed-off-by: default avatardmitry pervushin <dpervushin@embeddedalley.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent b4380b8e

arch/arm/mach-stmp378x/include/mach/regs-apbh.h

+79 −66
Original line number Diff line number Diff line 
/*

 * STMP APBH Register Definitions

 * stmp378x: APBH register definitions

 *

 * Copyright (c) 2008 Freescale Semiconductor

 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.

 *

 *

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or
@@ -20,69 +18,84 @@ 
 * along with this program; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA

 */

#ifndef _MACH_REGS_APBH

#define _MACH_REGS_APBH



#ifndef __ARCH_ARM___APBH_H

#define __ARCH_ARM___APBH_H  1



#include <mach/stmp3xxx_regs.h>

#define REGS_APBH_BASE	(STMP3XXX_REGS_BASE + 0x4000)

#define REGS_APBH_PHYS	0x80004000

#define REGS_APBH_SIZE	0x2000



#define REGS_APBH_BASE (REGS_BASE + 0x4000)

#define REGS_APBH_BASE_PHYS (0x80004000)

#define REGS_APBH_SIZE 0x00002000

HW_REGISTER(HW_APBH_CTRL0, REGS_APBH_BASE, 0x00000000)

#define HW_APBH_CTRL0_ADDR (REGS_APBH_BASE + 0x00000000)

#define BM_APBH_CTRL0_SFTRST 0x80000000

#define BM_APBH_CTRL0_CLKGATE 0x40000000

#define BM_APBH_CTRL0_AHB_BURST8_EN 0x20000000

#define BM_APBH_CTRL0_APB_BURST4_EN 0x10000000

#define BP_APBH_CTRL0_RESET_CHANNEL      16

#define HW_APBH_CTRL0		0x0

#define BM_APBH_CTRL0_RESET_CHANNEL	0x00FF0000

#define BF_APBH_CTRL0_RESET_CHANNEL(v)  \

	(((v) << 16) & BM_APBH_CTRL0_RESET_CHANNEL)

HW_REGISTER(HW_APBH_CTRL1, REGS_APBH_BASE, 0x00000010)

#define HW_APBH_CTRL1_ADDR (REGS_APBH_BASE + 0x00000010)

HW_REGISTER(HW_APBH_CTRL2, REGS_APBH_BASE, 0x00000020)

HW_REGISTER_0(HW_APBH_DEVSEL, REGS_APBH_BASE, 0x00000030)

HW_REGISTER_0_INDEXED(HW_APBH_CHn_CURCMDAR, REGS_APBH_BASE, 0x00000040, 0x70)

#define BP_APBH_CHn_CURCMDAR_CMD_ADDR      0

#define BM_APBH_CHn_CURCMDAR_CMD_ADDR 0xFFFFFFFF

#define BF_APBH_CHn_CURCMDAR_CMD_ADDR(v)   (v)

HW_REGISTER_0_INDEXED(HW_APBH_CHn_NXTCMDAR, REGS_APBH_BASE, 0x00000050, 0x70)

HW_REGISTER_0_INDEXED(HW_APBH_CHn_CMD, REGS_APBH_BASE, 0x00000060, 0x70)

#define BP_APBH_CHn_CMD_XFER_COUNT      16

#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000

#define BF_APBH_CHn_CMD_XFER_COUNT(v) \

	(((v) << 16) & BM_APBH_CHn_CMD_XFER_COUNT)

#define BP_APBH_CHn_CMD_CMDWORDS      12

#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000

#define BF_APBH_CHn_CMD_CMDWORDS(v)  \

	(((v) << 12) & BM_APBH_CHn_CMD_CMDWORDS)

#define BM_APBH_CHn_CMD_HALTONTERMINATE 0x00000100

#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080

#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040

#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020

#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010

#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008

#define BM_APBH_CHn_CMD_CHAIN 0x00000004

#define BP_APBH_CHn_CMD_COMMAND      0

#define BP_APBH_CTRL0_RESET_CHANNEL	16

#define BM_APBH_CTRL0_CLKGATE	0x40000000

#define BM_APBH_CTRL0_SFTRST	0x80000000



#define HW_APBH_CTRL1		0x10

#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ	0x00000001

#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ	0



#define HW_APBH_CTRL2		0x20



#define HW_APBH_DEVSEL		0x30



#define HW_APBH_CH0_NXTCMDAR	(0x50 + 0 * 0x70)

#define HW_APBH_CH1_NXTCMDAR	(0x50 + 1 * 0x70)

#define HW_APBH_CH2_NXTCMDAR	(0x50 + 2 * 0x70)

#define HW_APBH_CH3_NXTCMDAR	(0x50 + 3 * 0x70)

#define HW_APBH_CH4_NXTCMDAR	(0x50 + 4 * 0x70)

#define HW_APBH_CH5_NXTCMDAR	(0x50 + 5 * 0x70)

#define HW_APBH_CH6_NXTCMDAR	(0x50 + 6 * 0x70)

#define HW_APBH_CH7_NXTCMDAR	(0x50 + 7 * 0x70)

#define HW_APBH_CH8_NXTCMDAR	(0x50 + 8 * 0x70)

#define HW_APBH_CH9_NXTCMDAR	(0x50 + 9 * 0x70)

#define HW_APBH_CH10_NXTCMDAR	(0x50 + 10 * 0x70)

#define HW_APBH_CH11_NXTCMDAR	(0x50 + 11 * 0x70)

#define HW_APBH_CH12_NXTCMDAR	(0x50 + 12 * 0x70)

#define HW_APBH_CH13_NXTCMDAR	(0x50 + 13 * 0x70)

#define HW_APBH_CH14_NXTCMDAR	(0x50 + 14 * 0x70)

#define HW_APBH_CH15_NXTCMDAR	(0x50 + 15 * 0x70)



#define HW_APBH_CHn_NXTCMDAR	0x50



#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER	 0

#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE	 1

#define BV_APBH_CHn_CMD_COMMAND__DMA_READ	 2

#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE	 3

#define BM_APBH_CHn_CMD_COMMAND	0x00000003

#define BF_APBH_CHn_CMD_COMMAND(v)  \

	(((v) << 0) & BM_APBH_CHn_CMD_COMMAND)

#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0x0

#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE   0x1

#define BV_APBH_CHn_CMD_COMMAND__DMA_READ    0x2

#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE   0x3

HW_REGISTER_0_INDEXED(HW_APBH_CHn_BAR, REGS_APBH_BASE, 0x00000070, 0x70)

HW_REGISTER_0_INDEXED(HW_APBH_CHn_SEMA, REGS_APBH_BASE, 0x00000080, 0x70)

#define BP_APBH_CHn_SEMA_PHORE      16

#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000

#define BF_APBH_CHn_SEMA_PHORE(v)  \

	(((v) << 16) & BM_APBH_CHn_SEMA_PHORE)

#define BP_APBH_CHn_SEMA_INCREMENT_SEMA      0

#define BP_APBH_CHn_CMD_COMMAND	0

#define BM_APBH_CHn_CMD_CHAIN	0x00000004

#define BM_APBH_CHn_CMD_IRQONCMPLT	0x00000008

#define BM_APBH_CHn_CMD_NANDLOCK	0x00000010

#define BM_APBH_CHn_CMD_NANDWAIT4READY	0x00000020

#define BM_APBH_CHn_CMD_SEMAPHORE	0x00000040

#define BM_APBH_CHn_CMD_WAIT4ENDCMD	0x00000080

#define BM_APBH_CHn_CMD_CMDWORDS	0x0000F000

#define BP_APBH_CHn_CMD_CMDWORDS	12

#define BM_APBH_CHn_CMD_XFER_COUNT	0xFFFF0000

#define BP_APBH_CHn_CMD_XFER_COUNT	16



#define HW_APBH_CH0_SEMA	(0x80 + 0 * 0x70)

#define HW_APBH_CH1_SEMA	(0x80 + 1 * 0x70)

#define HW_APBH_CH2_SEMA	(0x80 + 2 * 0x70)

#define HW_APBH_CH3_SEMA	(0x80 + 3 * 0x70)

#define HW_APBH_CH4_SEMA	(0x80 + 4 * 0x70)

#define HW_APBH_CH5_SEMA	(0x80 + 5 * 0x70)

#define HW_APBH_CH6_SEMA	(0x80 + 6 * 0x70)

#define HW_APBH_CH7_SEMA	(0x80 + 7 * 0x70)

#define HW_APBH_CH8_SEMA	(0x80 + 8 * 0x70)

#define HW_APBH_CH9_SEMA	(0x80 + 9 * 0x70)

#define HW_APBH_CH10_SEMA	(0x80 + 10 * 0x70)

#define HW_APBH_CH11_SEMA	(0x80 + 11 * 0x70)

#define HW_APBH_CH12_SEMA	(0x80 + 12 * 0x70)

#define HW_APBH_CH13_SEMA	(0x80 + 13 * 0x70)

#define HW_APBH_CH14_SEMA	(0x80 + 14 * 0x70)

#define HW_APBH_CH15_SEMA	(0x80 + 15 * 0x70)



#define HW_APBH_CHn_SEMA	0x80

#define BM_APBH_CHn_SEMA_INCREMENT_SEMA	0x000000FF

#define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v)  \

	(((v) << 0) & BM_APBH_CHn_SEMA_INCREMENT_SEMA)

HW_REGISTER_0_INDEXED(HW_APBH_CHn_DEBUG1, REGS_APBH_BASE, 0x00000090, 0x70)

HW_REGISTER_0_INDEXED(HW_APBH_CHn_DEBUG2, REGS_APBH_BASE, 0x000000a0, 0x70)

HW_REGISTER_0(HW_APBH_VERSION, REGS_APBH_BASE, 0x000003f0)

#endif /* __ARCH_ARM___APBH_H */
 
#define BP_APBH_CHn_SEMA_INCREMENT_SEMA	0

#define BM_APBH_CHn_SEMA_PHORE	0x00FF0000

#define BP_APBH_CHn_SEMA_PHORE	16



#endif

arch/arm/mach-stmp378x/include/mach/regs-apbx.h

+98 −58
Original line number Diff line number Diff line 
/*

 * STMP APBX Register Definitions

 * stmp378x: APBX register definitions

 *

 * Copyright (c) 2008 Freescale Semiconductor

 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.

 *

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or
@@ -19,61 +18,102 @@ 
 * along with this program; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA

 */

#ifndef __ARCH_ARM___APBX_H

#define __ARCH_ARM___APBX_H  1

#ifndef _MACH_REGS_APBX

#define _MACH_REGS_APBX



#include <mach/stmp3xxx_regs.h>

#define REGS_APBX_BASE	(STMP3XXX_REGS_BASE + 0x24000)

#define REGS_APBX_PHYS	0x80024000

#define REGS_APBX_SIZE	0x2000



#define REGS_APBX_BASE (REGS_BASE + 0x24000)

#define REGS_APBX_BASE_PHYS (0x80024000)

#define REGS_APBX_SIZE 0x00002000

HW_REGISTER(HW_APBX_CTRL0, REGS_APBX_BASE, 0x00000000)

#define HW_APBX_CTRL0_ADDR (REGS_APBX_BASE + 0x00000000)

#define BM_APBX_CTRL0_SFTRST 0x80000000

#define HW_APBX_CTRL0		0x0

#define BM_APBX_CTRL0_CLKGATE	0x40000000

HW_REGISTER(HW_APBX_CTRL1, REGS_APBX_BASE, 0x00000010)

HW_REGISTER(HW_APBX_CTRL2, REGS_APBX_BASE, 0x00000020)

HW_REGISTER(HW_APBX_CHANNEL_CTRL, REGS_APBX_BASE, 0x00000030)

#define BP_APBX_CHANNEL_CTRL_RESET_CHANNEL      16

#define BM_APBX_CTRL0_SFTRST	0x80000000



#define HW_APBX_CTRL1		0x10



#define HW_APBX_CTRL2		0x20



#define HW_APBX_CHANNEL_CTRL	0x30

#define BM_APBX_CHANNEL_CTRL_RESET_CHANNEL	0xFFFF0000

#define BF_APBX_CHANNEL_CTRL_RESET_CHANNEL(v)   \

	(((v) << BP_APBX_CHANNEL_CTRL_RESET_CHANNEL) & \

	 BM_APBX_CHANNEL_CTRL_RESET_CHANNEL)

HW_REGISTER_0(HW_APBX_DEVSEL, REGS_APBX_BASE, 0x00000040)

HW_REGISTER_0_INDEXED(HW_APBX_CHn_CURCMDAR, REGS_APBX_BASE, 0x00000100, 0x70)

HW_REGISTER_0_INDEXED(HW_APBX_CHn_NXTCMDAR, REGS_APBX_BASE, 0x00000110, 0x70)

HW_REGISTER_0_INDEXED(HW_APBX_CHn_CMD, REGS_APBX_BASE, 0x00000120, 0x70)

#define BP_APBX_CHn_CMD_XFER_COUNT      16

#define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000

#define BF_APBX_CHn_CMD_XFER_COUNT(v) \

	(((v) << 16) & BM_APBX_CHn_CMD_XFER_COUNT)

#define BP_APBX_CHn_CMD_CMDWORDS      12

#define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000

#define BF_APBX_CHn_CMD_CMDWORDS(v)  \

	(((v) << 12) & BM_APBX_CHn_CMD_CMDWORDS)

#define BM_APBX_CHn_CMD_HALTONTERMINATE 0x00000100

#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080

#define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040

#define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008

#define BM_APBX_CHn_CMD_CHAIN 0x00000004

#define BP_APBX_CHn_CMD_COMMAND      0

#define BP_APBX_CHANNEL_CTRL_RESET_CHANNEL	16



#define HW_APBX_DEVSEL		0x40



#define HW_APBX_CH0_NXTCMDAR	(0x110 + 0 * 0x70)

#define HW_APBX_CH1_NXTCMDAR	(0x110 + 1 * 0x70)

#define HW_APBX_CH2_NXTCMDAR	(0x110 + 2 * 0x70)

#define HW_APBX_CH3_NXTCMDAR	(0x110 + 3 * 0x70)

#define HW_APBX_CH4_NXTCMDAR	(0x110 + 4 * 0x70)

#define HW_APBX_CH5_NXTCMDAR	(0x110 + 5 * 0x70)

#define HW_APBX_CH6_NXTCMDAR	(0x110 + 6 * 0x70)

#define HW_APBX_CH7_NXTCMDAR	(0x110 + 7 * 0x70)

#define HW_APBX_CH8_NXTCMDAR	(0x110 + 8 * 0x70)

#define HW_APBX_CH9_NXTCMDAR	(0x110 + 9 * 0x70)

#define HW_APBX_CH10_NXTCMDAR	(0x110 + 10 * 0x70)

#define HW_APBX_CH11_NXTCMDAR	(0x110 + 11 * 0x70)

#define HW_APBX_CH12_NXTCMDAR	(0x110 + 12 * 0x70)

#define HW_APBX_CH13_NXTCMDAR	(0x110 + 13 * 0x70)

#define HW_APBX_CH14_NXTCMDAR	(0x110 + 14 * 0x70)

#define HW_APBX_CH15_NXTCMDAR	(0x110 + 15 * 0x70)



#define HW_APBX_CHn_NXTCMDAR	0x110

#define BM_APBX_CHn_CMD_COMMAND	0x00000003

#define BF_APBX_CHn_CMD_COMMAND(v)  \

	(((v) << 0) & BM_APBX_CHn_CMD_COMMAND)

#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER 0x0

#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE   0x1

#define BV_APBX_CHn_CMD_COMMAND__DMA_READ    0x2

HW_REGISTER_0_INDEXED(HW_APBX_CHn_BAR, REGS_APBX_BASE, 0x00000130, 0x70)

HW_REGISTER_0_INDEXED(HW_APBX_CHn_SEMA, REGS_APBX_BASE, 0x00000140, 0x70)

#define BP_APBX_CHn_SEMA_PHORE      16

#define BM_APBX_CHn_SEMA_PHORE 0x00FF0000

#define BF_APBX_CHn_SEMA_PHORE(v)  \

	(((v) << 16) & BM_APBX_CHn_SEMA_PHORE)

#define BP_APBX_CHn_SEMA_INCREMENT_SEMA      0

#define BP_APBX_CHn_CMD_COMMAND	0

#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER	 0

#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE	 1

#define BV_APBX_CHn_CMD_COMMAND__DMA_READ	 2

#define BV_APBX_CHn_CMD_COMMAND__DMA_SENSE	 3

#define BM_APBX_CHn_CMD_CHAIN	0x00000004

#define BM_APBX_CHn_CMD_IRQONCMPLT	0x00000008

#define BM_APBX_CHn_CMD_SEMAPHORE	0x00000040

#define BM_APBX_CHn_CMD_WAIT4ENDCMD	0x00000080

#define BM_APBX_CHn_CMD_HALTONTERMINATE	0x00000100

#define BM_APBX_CHn_CMD_CMDWORDS	0x0000F000

#define BP_APBX_CHn_CMD_CMDWORDS	12

#define BM_APBX_CHn_CMD_XFER_COUNT	0xFFFF0000

#define BP_APBX_CHn_CMD_XFER_COUNT	16



#define HW_APBX_CH0_BAR		(0x130 + 0 * 0x70)

#define HW_APBX_CH1_BAR		(0x130 + 1 * 0x70)

#define HW_APBX_CH2_BAR		(0x130 + 2 * 0x70)

#define HW_APBX_CH3_BAR		(0x130 + 3 * 0x70)

#define HW_APBX_CH4_BAR		(0x130 + 4 * 0x70)

#define HW_APBX_CH5_BAR		(0x130 + 5 * 0x70)

#define HW_APBX_CH6_BAR		(0x130 + 6 * 0x70)

#define HW_APBX_CH7_BAR		(0x130 + 7 * 0x70)

#define HW_APBX_CH8_BAR		(0x130 + 8 * 0x70)

#define HW_APBX_CH9_BAR		(0x130 + 9 * 0x70)

#define HW_APBX_CH10_BAR		(0x130 + 10 * 0x70)

#define HW_APBX_CH11_BAR		(0x130 + 11 * 0x70)

#define HW_APBX_CH12_BAR		(0x130 + 12 * 0x70)

#define HW_APBX_CH13_BAR		(0x130 + 13 * 0x70)

#define HW_APBX_CH14_BAR		(0x130 + 14 * 0x70)

#define HW_APBX_CH15_BAR		(0x130 + 15 * 0x70)



#define HW_APBX_CHn_BAR		0x130



#define HW_APBX_CH0_SEMA	(0x140 + 0 * 0x70)

#define HW_APBX_CH1_SEMA	(0x140 + 1 * 0x70)

#define HW_APBX_CH2_SEMA	(0x140 + 2 * 0x70)

#define HW_APBX_CH3_SEMA	(0x140 + 3 * 0x70)

#define HW_APBX_CH4_SEMA	(0x140 + 4 * 0x70)

#define HW_APBX_CH5_SEMA	(0x140 + 5 * 0x70)

#define HW_APBX_CH6_SEMA	(0x140 + 6 * 0x70)

#define HW_APBX_CH7_SEMA	(0x140 + 7 * 0x70)

#define HW_APBX_CH8_SEMA	(0x140 + 8 * 0x70)

#define HW_APBX_CH9_SEMA	(0x140 + 9 * 0x70)

#define HW_APBX_CH10_SEMA	(0x140 + 10 * 0x70)

#define HW_APBX_CH11_SEMA	(0x140 + 11 * 0x70)

#define HW_APBX_CH12_SEMA	(0x140 + 12 * 0x70)

#define HW_APBX_CH13_SEMA	(0x140 + 13 * 0x70)

#define HW_APBX_CH14_SEMA	(0x140 + 14 * 0x70)

#define HW_APBX_CH15_SEMA	(0x140 + 15 * 0x70)



#define HW_APBX_CHn_SEMA	0x140

#define BM_APBX_CHn_SEMA_INCREMENT_SEMA	0x000000FF

#define BF_APBX_CHn_SEMA_INCREMENT_SEMA(v)  \

	(((v) << 0) & BM_APBX_CHn_SEMA_INCREMENT_SEMA)

HW_REGISTER_0_INDEXED(HW_APBX_CHn_DEBUG1, REGS_APBX_BASE, 0x00000150, 0x70)

HW_REGISTER_0_INDEXED(HW_APBX_CHn_DEBUG2, REGS_APBX_BASE, 0x00000160, 0x70)

HW_REGISTER_0(HW_APBX_VERSION, REGS_APBX_BASE, 0x00000800)

#endif /* __ARCH_ARM___APBX_H */
 
#define BP_APBX_CHn_SEMA_INCREMENT_SEMA	0

#define BM_APBX_CHn_SEMA_PHORE	0x00FF0000

#define BP_APBX_CHn_SEMA_PHORE	16



#endif

arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h

+66 −254

File changed.

Preview size limit exceeded, changes collapsed.

arch/arm/mach-stmp378x/include/mach/regs-icoll.h

+23 −191
Original line number Diff line number Diff line 
/*

 * STMP ICOLL Register Definitions

 * stmp378x: ICOLL register definitions

 *

 * Copyright (c) 2008 Freescale Semiconductor

 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
@@ -18,196 +18,28 @@ 
 * along with this program; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA

 */

#ifndef _MACH_REGS_ICOLL

#define _MACH_REGS_ICOLL



#ifndef __ARCH_ARM___ICOLL_H

#define __ARCH_ARM___ICOLL_H  1

#define REGS_ICOLL_BASE	(STMP3XXX_REGS_BASE + 0x0)

#define REGS_ICOLL_PHYS	0x80000000

#define REGS_ICOLL_SIZE	0x2000



#include <mach/stmp3xxx_regs.h>

#define HW_ICOLL_VECTOR		0x0



#define REGS_ICOLL_BASE (REGS_BASE + 0x0)

#define REGS_ICOLL_BASE_PHYS (0x80000000)

#define REGS_ICOLL_SIZE 0x00002000

HW_REGISTER(HW_ICOLL_VECTOR, REGS_ICOLL_BASE, 0x00000000)

#define HW_ICOLL_VECTOR_ADDR (REGS_ICOLL_BASE + 0x00000000)

#define BP_ICOLL_VECTOR_IRQVECTOR      2

#define BM_ICOLL_VECTOR_IRQVECTOR 0xFFFFFFFC

#define BF_ICOLL_VECTOR_IRQVECTOR(v) \

	(((v) << 2) & BM_ICOLL_VECTOR_IRQVECTOR)

HW_REGISTER_0(HW_ICOLL_LEVELACK, REGS_ICOLL_BASE, 0x00000010)

#define HW_ICOLL_LEVELACK_ADDR (REGS_ICOLL_BASE + 0x00000010)

#define BP_ICOLL_LEVELACK_IRQLEVELACK      0

#define HW_ICOLL_LEVELACK	0x10

#define BM_ICOLL_LEVELACK_IRQLEVELACK	0x0000000F

#define BF_ICOLL_LEVELACK_IRQLEVELACK(v)  \

	(((v) << 0) & BM_ICOLL_LEVELACK_IRQLEVELACK)

#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1

#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL1 0x2

#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL2 0x4

#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL3 0x8

HW_REGISTER(HW_ICOLL_CTRL, REGS_ICOLL_BASE, 0x00000020)

#define HW_ICOLL_CTRL_ADDR (REGS_ICOLL_BASE + 0x00000020)

#define BM_ICOLL_CTRL_SFTRST 0x80000000

#define BV_ICOLL_CTRL_SFTRST__RUN      0x0

#define BV_ICOLL_CTRL_SFTRST__IN_RESET 0x1

#define BP_ICOLL_LEVELACK_IRQLEVELACK	0



#define HW_ICOLL_CTRL		0x20

#define BM_ICOLL_CTRL_CLKGATE	0x40000000

#define BV_ICOLL_CTRL_CLKGATE__RUN       0x0

#define BV_ICOLL_CTRL_CLKGATE__NO_CLOCKS 0x1

#define BP_ICOLL_CTRL_VECTOR_PITCH      21

#define BM_ICOLL_CTRL_VECTOR_PITCH 0x00E00000

#define BF_ICOLL_CTRL_VECTOR_PITCH(v)  \

	(((v) << 21) & BM_ICOLL_CTRL_VECTOR_PITCH)

#define BV_ICOLL_CTRL_VECTOR_PITCH__DEFAULT_BY4 0x0

#define BV_ICOLL_CTRL_VECTOR_PITCH__BY4	 0x1

#define BV_ICOLL_CTRL_VECTOR_PITCH__BY8	 0x2

#define BV_ICOLL_CTRL_VECTOR_PITCH__BY12	0x3

#define BV_ICOLL_CTRL_VECTOR_PITCH__BY16	0x4

#define BV_ICOLL_CTRL_VECTOR_PITCH__BY20	0x5

#define BV_ICOLL_CTRL_VECTOR_PITCH__BY24	0x6

#define BV_ICOLL_CTRL_VECTOR_PITCH__BY28	0x7

#define BM_ICOLL_CTRL_BYPASS_FSM 0x00100000

#define BV_ICOLL_CTRL_BYPASS_FSM__NORMAL 0x0

#define BV_ICOLL_CTRL_BYPASS_FSM__BYPASS 0x1

#define BM_ICOLL_CTRL_NO_NESTING 0x00080000

#define BV_ICOLL_CTRL_NO_NESTING__NORMAL  0x0

#define BV_ICOLL_CTRL_NO_NESTING__NO_NEST 0x1

#define BM_ICOLL_CTRL_ARM_RSE_MODE 0x00040000

#define BM_ICOLL_CTRL_FIQ_FINAL_ENABLE 0x00020000

#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__DISABLE 0x0

#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__ENABLE  0x1

#define BM_ICOLL_CTRL_IRQ_FINAL_ENABLE 0x00010000

#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__DISABLE 0x0

#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__ENABLE  0x1

HW_REGISTER(HW_ICOLL_VBASE, REGS_ICOLL_BASE, 0x00000040)

#define HW_ICOLL_VBASE_ADDR (REGS_ICOLL_BASE + 0x00000040)

#define BP_ICOLL_VBASE_TABLE_ADDRESS      2

#define BM_ICOLL_VBASE_TABLE_ADDRESS 0xFFFFFFFC

#define BF_ICOLL_VBASE_TABLE_ADDRESS(v) \

	(((v) << 2) & BM_ICOLL_VBASE_TABLE_ADDRESS)

HW_REGISTER_0(HW_ICOLL_STAT, REGS_ICOLL_BASE, 0x00000070)

#define HW_ICOLL_STAT_ADDR (REGS_ICOLL_BASE + 0x00000070)

#define BP_ICOLL_STAT_VECTOR_NUMBER      0

#define BM_ICOLL_STAT_VECTOR_NUMBER 0x0000007F

#define BF_ICOLL_STAT_VECTOR_NUMBER(v)  \

	(((v) << 0) & BM_ICOLL_STAT_VECTOR_NUMBER)

/*

 *  multi-register-define name HW_ICOLL_RAWn

 *	      base 0x000000A0

 *	      count 4

 *	      offset 0x10

 */

HW_REGISTER_0_INDEXED(HW_ICOLL_RAWn, REGS_ICOLL_BASE, 0x000000a0, 0x10)

#define BP_ICOLL_RAWn_RAW_IRQS      0

#define BM_ICOLL_RAWn_RAW_IRQS 0xFFFFFFFF

#define BF_ICOLL_RAWn_RAW_IRQS(v)   (v)

/*

 *  multi-register-define name HW_ICOLL_INTERRUPTn

 *	      base 0x00000120

 *	      count 128

 *	      offset 0x10

 */

HW_REGISTER_INDEXED(HW_ICOLL_INTERRUPTn, REGS_ICOLL_BASE, 0x00000120, 0x10)

#define BM_ICOLL_INTERRUPTn_ENFIQ 0x00000010

#define BV_ICOLL_INTERRUPTn_ENFIQ__DISABLE 0x0

#define BV_ICOLL_INTERRUPTn_ENFIQ__ENABLE  0x1

#define BM_ICOLL_INTERRUPTn_SOFTIRQ 0x00000008

#define BV_ICOLL_INTERRUPTn_SOFTIRQ__NO_INTERRUPT    0x0

#define BV_ICOLL_INTERRUPTn_SOFTIRQ__FORCE_INTERRUPT 0x1

#define BM_ICOLL_CTRL_SFTRST	0x80000000



#define HW_ICOLL_STAT		0x70



#define HW_ICOLL_INTERRUPTn	0x120



#define HW_ICOLL_INTERRUPTn	0x120

#define BM_ICOLL_INTERRUPTn_ENABLE	0x00000004

#define BV_ICOLL_INTERRUPTn_ENABLE__DISABLE 0x0

#define BV_ICOLL_INTERRUPTn_ENABLE__ENABLE  0x1

#define BP_ICOLL_INTERRUPTn_PRIORITY      0

#define BM_ICOLL_INTERRUPTn_PRIORITY 0x00000003

#define BF_ICOLL_INTERRUPTn_PRIORITY(v)  \

	(((v) << 0) & BM_ICOLL_INTERRUPTn_PRIORITY)

#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL0 0x0

#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL1 0x1

#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL2 0x2

#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL3 0x3

HW_REGISTER(HW_ICOLL_DEBUG, REGS_ICOLL_BASE, 0x00001120)

#define HW_ICOLL_DEBUG_ADDR (REGS_ICOLL_BASE + 0x00001120)

#define BP_ICOLL_DEBUG_INSERVICE      28

#define BM_ICOLL_DEBUG_INSERVICE 0xF0000000

#define BF_ICOLL_DEBUG_INSERVICE(v) \

	(((v) << 28) & BM_ICOLL_DEBUG_INSERVICE)

#define BV_ICOLL_DEBUG_INSERVICE__LEVEL0 0x1

#define BV_ICOLL_DEBUG_INSERVICE__LEVEL1 0x2

#define BV_ICOLL_DEBUG_INSERVICE__LEVEL2 0x4

#define BV_ICOLL_DEBUG_INSERVICE__LEVEL3 0x8

#define BP_ICOLL_DEBUG_LEVEL_REQUESTS      24

#define BM_ICOLL_DEBUG_LEVEL_REQUESTS 0x0F000000

#define BF_ICOLL_DEBUG_LEVEL_REQUESTS(v)  \

	(((v) << 24) & BM_ICOLL_DEBUG_LEVEL_REQUESTS)

#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL0 0x1

#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL1 0x2

#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL2 0x4

#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL3 0x8

#define BP_ICOLL_DEBUG_REQUESTS_BY_LEVEL      20

#define BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL 0x00F00000

#define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL(v)  \

	(((v) << 20) & BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL)

#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL0 0x1

#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL1 0x2

#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL2 0x4

#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL3 0x8

#define BM_ICOLL_DEBUG_FIQ 0x00020000

#define BV_ICOLL_DEBUG_FIQ__NO_FIQ_REQUESTED 0x0

#define BV_ICOLL_DEBUG_FIQ__FIQ_REQUESTED    0x1

#define BM_ICOLL_DEBUG_IRQ 0x00010000

#define BV_ICOLL_DEBUG_IRQ__NO_IRQ_REQUESTED 0x0

#define BV_ICOLL_DEBUG_IRQ__IRQ_REQUESTED    0x1

#define BP_ICOLL_DEBUG_VECTOR_FSM      0

#define BM_ICOLL_DEBUG_VECTOR_FSM 0x000003FF

#define BF_ICOLL_DEBUG_VECTOR_FSM(v)  \

	(((v) << 0) & BM_ICOLL_DEBUG_VECTOR_FSM)

#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_IDLE	 0x000

#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE1  0x001

#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE2  0x002

#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_PENDING      0x004

#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE3  0x008

#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE4  0x010

#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING1 0x020

#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING2 0x040

#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING3 0x080

#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE5  0x100

#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE6  0x200

HW_REGISTER(HW_ICOLL_DBGREAD0, REGS_ICOLL_BASE, 0x00001130)

#define HW_ICOLL_DBGREAD0_ADDR (REGS_ICOLL_BASE + 0x00001130)

#define BP_ICOLL_DBGREAD0_VALUE      0

#define BM_ICOLL_DBGREAD0_VALUE 0xFFFFFFFF

#define BF_ICOLL_DBGREAD0_VALUE(v)   (v)

HW_REGISTER(HW_ICOLL_DBGREAD1, REGS_ICOLL_BASE, 0x00001140)

#define HW_ICOLL_DBGREAD1_ADDR (REGS_ICOLL_BASE + 0x00001140)

#define BP_ICOLL_DBGREAD1_VALUE      0

#define BM_ICOLL_DBGREAD1_VALUE 0xFFFFFFFF

#define BF_ICOLL_DBGREAD1_VALUE(v)   (v)

HW_REGISTER(HW_ICOLL_DBGFLAG, REGS_ICOLL_BASE, 0x00001150)

#define HW_ICOLL_DBGFLAG_ADDR (REGS_ICOLL_BASE + 0x00001150)

#define BP_ICOLL_DBGFLAG_FLAG      0

#define BM_ICOLL_DBGFLAG_FLAG 0x0000FFFF

#define BF_ICOLL_DBGFLAG_FLAG(v)  \

	(((v) << 0) & BM_ICOLL_DBGFLAG_FLAG)

/*

 *  multi-register-define name HW_ICOLL_DBGREQUESTn

 *	      base 0x00001160

 *	      count 4

 *	      offset 0x10

 */

HW_REGISTER_0_INDEXED(HW_ICOLL_DBGREQUESTn, REGS_ICOLL_BASE, 0x00001160,

		       0x10)

#define BP_ICOLL_DBGREQUESTn_BITS      0

#define BM_ICOLL_DBGREQUESTn_BITS 0xFFFFFFFF

#define BF_ICOLL_DBGREQUESTn_BITS(v)   (v)

HW_REGISTER_0(HW_ICOLL_VERSION, REGS_ICOLL_BASE, 0x000011e0)

#define HW_ICOLL_VERSION_ADDR (REGS_ICOLL_BASE + 0x000011e0)

#define BP_ICOLL_VERSION_MAJOR      24

#define BM_ICOLL_VERSION_MAJOR 0xFF000000

#define BF_ICOLL_VERSION_MAJOR(v) \

	(((v) << 24) & BM_ICOLL_VERSION_MAJOR)

#define BP_ICOLL_VERSION_MINOR      16

#define BM_ICOLL_VERSION_MINOR 0x00FF0000

#define BF_ICOLL_VERSION_MINOR(v)  \

	(((v) << 16) & BM_ICOLL_VERSION_MINOR)

#define BP_ICOLL_VERSION_STEP      0

#define BM_ICOLL_VERSION_STEP 0x0000FFFF

#define BF_ICOLL_VERSION_STEP(v)  \

	(((v) << 0) & BM_ICOLL_VERSION_STEP)

#endif /* __ARCH_ARM___ICOLL_H */
 


#endif

arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h

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