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Commit e0288e5b authored by Sarangdhar Joshi's avatar Sarangdhar Joshi Committed by Matt Wagantall
Browse files

ARM: dts: msm: enable support to avoid etm trace overflow 



ETM trace overflow in certain conditions is not supported on
msm8996 v1 and v2. Enable support to avoid this ETM trace
overflow condition.

Change-Id: Ie354a91385577ebea79d29e7ede1655c830652fa
Signed-off-by: default avatarSarangdhar Joshi <spjoshi@codeaurora.org>
parent 77245b6f

arch/arm/boot/dts/qcom/msm8996-coresight-v1.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -432,6 +432,8 @@ 
		coresight-child-ports = <0>;

		coresight-etm-cpu = <&CPU0>;



		qcom,noovrflw-enable;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";
@@ -450,6 +452,8 @@ 
		coresight-child-ports = <1>;

		coresight-etm-cpu = <&CPU1>;



		qcom,noovrflw-enable;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";
@@ -468,6 +472,8 @@ 
		coresight-child-ports = <0>;

		coresight-etm-cpu = <&CPU2>;



		qcom,noovrflw-enable;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";
@@ -486,6 +492,8 @@ 
		coresight-child-ports = <1>;

		coresight-etm-cpu = <&CPU3>;



		qcom,noovrflw-enable;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

arch/arm/boot/dts/qcom/msm8996-coresight-v2.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -469,6 +469,8 @@ 
		coresight-child-ports = <0>;

		coresight-etm-cpu = <&CPU0>;



		qcom,noovrflw-enable;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";
@@ -487,6 +489,8 @@ 
		coresight-child-ports = <1>;

		coresight-etm-cpu = <&CPU1>;



		qcom,noovrflw-enable;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";
@@ -505,6 +509,8 @@ 
		coresight-child-ports = <0>;

		coresight-etm-cpu = <&CPU2>;



		qcom,noovrflw-enable;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";
@@ -523,6 +529,8 @@ 
		coresight-child-ports = <1>;

		coresight-etm-cpu = <&CPU3>;



		qcom,noovrflw-enable;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";