msm: jpeg: dma: Add dynamic clock scaling to jpeg dma v4l2 driver

- camss-vdd-supply: phandle to GDSC regulator controlling camss.

- clock-names : names of clocks required for the device.

- clocks : clocks required for the device.

- clock-rates: should specify clock rates in Hz to each clocks

- qcom,clock-rates: should specify clock rates in Hz to each clocks

    property defined.

Optional properties:

- qos-regs: relative address offsets of QoS registers.

- qos-settings: QoS values to be written to QoS registers.

- vbif-regs: relative address offsets of VBIF registers.

- vbif-settings: VBIF values to be written to VBIF registers.

- qcom,qos-regs: relative address offsets of QoS registers.

- qcom,qos-settings: QoS values to be written to QoS registers.

- qcom,vbif-regs: relative address offsets of VBIF registers.

- qcom,vbif-settings: VBIF values to be written to VBIF registers.

Example:

	qcom,jpegdma@aa0000 {

			<&clock_mmss clk_mmss_mmagic_ahb_clk>,

			<&clock_mmss clk_mmss_mmagic_axi_clk>,

			<&clock_mmss clk_mmagic_camss_axi_clk>;

		clock-rates = <266670000 0 0 0 0 0 0 0 0>,

		qcom,clock-rates = <266670000 0 0 0 0 0 0 0 0>,

				<400000000 0 0 0 0 0 0 0 0>;

		vbif-regs = <0x4 0xDC 0x124 0x160>;

		vbif-settings = <0x1 0x7 0x1 0x22222222>;

		qcom,vbif-regs = <0x4 0xDC 0x124 0x160>;

		qcom,vbif-settings = <0x1 0x7 0x1 0x22222222>;

		status = "ok";

	};

	{

		.name = "Greyscale",

		.fourcc = V4L2_PIX_FMT_GREY,

		.depth = 8,

		.num_planes = 1,

		.colplane_h = 1,

		.colplane_v = 1,

	{

		.name = "Y/CbCr 4:2:0",

		.fourcc = V4L2_PIX_FMT_NV12,

		.depth = 12,

		.num_planes = 2,

		.colplane_h = 1,

		.colplane_v = 2,

	{

		.name = "Y/CrCb 4:2:0",

		.fourcc = V4L2_PIX_FMT_NV21,

		.depth = 12,

		.num_planes = 2,

		.colplane_h = 1,

		.colplane_v = 2,

	{

		.name = "YUV 4:2:0 planar, YCbCr",

		.fourcc = V4L2_PIX_FMT_YUV420,

		.depth = 12,

		.num_planes = 3,

		.colplane_h = 2,

		.colplane_v = 2,

	size->in_size.left = ctx->crop.left;

	size->in_size.width = ctx->crop.width;

	size->in_size.height = ctx->crop.height;

	size->in_size.real_height = ctx->format_out.fmt.pix.height;

	size->in_size.scanline = ctx->format_out.fmt.pix.height;

	size->in_size.stride = ctx->format_out.fmt.pix.bytesperline;

	size->out_size.top = 0;

	size->out_size.left = 0;

	size->out_size.width = ctx->format_cap.fmt.pix.width;

	size->out_size.height = ctx->format_cap.fmt.pix.height;

	size->out_size.real_height = ctx->format_cap.fmt.pix.height;

	size->out_size.scanline = ctx->format_cap.fmt.pix.height;

	size->out_size.stride = ctx->format_cap.fmt.pix.bytesperline;

}

	if (f->fmt.pix.height < MSM_JPEGDMA_MIN_HEIGHT)

		f->fmt.pix.height = MSM_JPEGDMA_MIN_HEIGHT;

	if (formats[format_idx].h_align)

	if (formats[format_idx].h_align > 1)

		f->fmt.pix.width &= ~(formats[format_idx].h_align - 1);

	if (formats[format_idx].v_align)

	if (formats[format_idx].v_align > 1)

		f->fmt.pix.height &= ~(formats[format_idx].v_align - 1);

	if (f->fmt.pix.bytesperline < f->fmt.pix.width)

	int ret = 0;

	if (msm_jpegdma_config_ok(ctx)) {

		mutex_lock(&ctx->lock);

		size.fps = ctx->timeperframe.denominator /

			ctx->timeperframe.numerator;

		size.format = formats[ctx->format_idx];

			dev_err(ctx->jdma_device->dev, "Can not get hw cfg\n");

		else

			ctx->pending_config = 1;

		mutex_unlock(&ctx->lock);

	}

	return ret;

	struct jpegdma_ctx *ctx = vb2_get_drv_priv(q);

	int ret;

	ret = msm_jpegdma_hw_get(ctx->jdma_device, ctx->speed);

	ret = msm_jpegdma_hw_get(ctx->jdma_device);

	if (ret < 0) {

		dev_err(ctx->jdma_device->dev, "Fail to get dma hw\n");

		return ret;

	}

	if (!atomic_read(&ctx->active)) {

		ret =  msm_jpegdma_update_hw_config(ctx);

		if (ret < 0) {

			dev_err(ctx->jdma_device->dev, "Fail to configure hw\n");

			return ret;

		}

		atomic_set(&ctx->active, 1);

	}

	return 0;

}

	mutex_init(&ctx->lock);

	ctx->jdma_device = device;

	dev_dbg(ctx->jdma_device->dev, "Jpeg v4l2 dma open\n");

	/* Set ctx defaults */

	ctx->speed = ctx->jdma_device->clk_rates_num - 1;

	ctx->timeperframe.numerator = 1;

	ctx->timeperframe.denominator = MSM_JPEGDMA_DEFAULT_FPS;

	atomic_set(&ctx->active, 0);

	v4l2_fh_init(&ctx->fh, video);

	}

	init_completion(&ctx->completion);

	complete_all(&ctx->completion);

	dev_dbg(ctx->jdma_device->dev, "Jpeg v4l2 dma open success\n");

	return 0;

error_m2m_init:

	ctx->format_cap = *f;

	return msm_jpegdma_update_hw_config(ctx);

	return 0;

}

/*

	ctx->format_out = *f;

	return msm_jpegdma_update_hw_config(ctx);

	return 0;

}

/*

	return ret;

}

/*

 * msm_jpegdma_guery_ctrl - V4l2 ioctl query control.

 * @file: Pointer to file struct.

 * @fh: V4l2 File handle.

 * @a: Pointer to v4l2_queryctrl struct info need to be filled based on id.

 */

static int msm_jpegdma_guery_ctrl(struct file *file, void *fh,

	struct v4l2_queryctrl *a)

{

	struct jpegdma_ctx *ctx = msm_jpegdma_ctx_from_fh(fh);

	switch (a->id) {

	case V4L2_CID_JPEG_DMA_SPEED:

		a->type = V4L2_CTRL_TYPE_INTEGER;

		a->default_value = ctx->jdma_device->clk_rates_num - 1;

		a->minimum = 0;

		a->maximum = ctx->jdma_device->clk_rates_num - 1;

		a->step = 1;

		strlcpy(a->name, "msm jpeg dma speed idx",

			sizeof(a->name));

		break;

	default:

		return -EINVAL;

	}

	return 0;

}

/*

 * msm_jpegdma_g_ctrl - V4l2 ioctl get control.

 * @file: Pointer to file struct.

 * @fh: V4l2 File handle.

 * @a: Pointer to v4l2_queryctrl struct need to be filled.

 */

static int msm_jpegdma_g_ctrl(struct file *file, void *fh,

	struct v4l2_control *a)

{

	struct jpegdma_ctx *ctx = msm_jpegdma_ctx_from_fh(fh);

	switch (a->id) {

	case V4L2_CID_JPEG_DMA_SPEED:

		a->value = ctx->speed;

		break;

	default:

		return -EINVAL;

	}

	return 0;

}

/*

 * msm_jpegdma_s_ctrl - V4l2 ioctl set control.

 * @file: Pointer to file struct.

 * @fh: V4l2 File handle.

 * @a: Pointer to v4l2_queryctrl struct need to be set.

 */

static int msm_jpegdma_s_ctrl(struct file *file, void *fh,

	struct v4l2_control *a)

{

	struct jpegdma_ctx *ctx = msm_jpegdma_ctx_from_fh(fh);

	switch (a->id) {

	case V4L2_CID_JPEG_DMA_SPEED:

		if (a->value > ctx->jdma_device->clk_rates_num - 1)

			a->value = ctx->jdma_device->clk_rates_num - 1;

		else if (a->value < 0)

			a->value = 0;

		ctx->speed = a->value;

		break;

	default:

		return -EINVAL;

	}

	return 0;

}

/*

 * msm_jpegdma_cropcap - V4l2 ioctl crop capabilites.

 * @file: Pointer to file struct.

		break;

	default:

		return -EINVAL;

	}

	return 0;

}

	const struct v4l2_crop *crop)

{

	struct jpegdma_ctx *ctx = msm_jpegdma_ctx_from_fh(fh);

	int ret = 0;

	/* Crop is supported only for input buffers */

	if (crop->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)

	if (crop->c.top % formats[ctx->format_idx].v_align)

		return -EINVAL;

	mutex_lock(&ctx->lock);

	ctx->crop = crop->c;

	if (atomic_read(&ctx->active))

		ret = msm_jpegdma_update_hw_config(ctx);

	mutex_unlock(&ctx->lock);

	return msm_jpegdma_update_hw_config(ctx);

	return ret;

}

/*

 * msm_jpegdma_g_crop - V4l2 ioctl get parm.

 * @file: Pointer to file struct.

 * @fh: V4l2 File handle.

 * @a: Pointer to v4l2_streamparm struct need to be filled.

 */

static int msm_jpegdma_g_parm(struct file *file, void *fh,

	struct v4l2_streamparm *a)

{

	struct jpegdma_ctx *ctx = msm_jpegdma_ctx_from_fh(fh);

	/* Get param is supported only for input buffers */

	if (a->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)

		return -EINVAL;

	a->parm.output.capability = 0;

	a->parm.output.extendedmode = 0;

	a->parm.output.outputmode = 0;

	a->parm.output.writebuffers = 0;

	a->parm.output.timeperframe = ctx->timeperframe;

	return 0;

}

/*

 * msm_jpegdma_s_crop - V4l2 ioctl set parm.

 * @file: Pointer to file struct.

 * @fh: V4l2 File handle.

 * @a: Pointer to v4l2_streamparm struct need to be set.

 */

static int msm_jpegdma_s_parm(struct file *file, void *fh,

	struct v4l2_streamparm *a)

{

	struct jpegdma_ctx *ctx = msm_jpegdma_ctx_from_fh(fh);

	/* Set param is supported only for input buffers */

	if (a->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)

		return -EINVAL;

	if (!a->parm.output.timeperframe.numerator ||

	    !a->parm.output.timeperframe.denominator)

		return -EINVAL;

	/* Frame rate is not supported during streaming */

	if (atomic_read(&ctx->active))

		return -EINVAL;

	ctx->timeperframe = a->parm.output.timeperframe;

	return 0;

}

/* V4l2 ioctl handlers */

	.vidioc_dqbuf             = msm_jpegdma_dqbuf,

	.vidioc_streamon          = msm_jpegdma_streamon,

	.vidioc_streamoff         = msm_jpegdma_streamoff,

	.vidioc_queryctrl         = msm_jpegdma_guery_ctrl,

	.vidioc_s_ctrl            = msm_jpegdma_s_ctrl,

	.vidioc_g_ctrl            = msm_jpegdma_g_ctrl,

	.vidioc_cropcap           = msm_jpegdma_cropcap,

	.vidioc_g_crop            = msm_jpegdma_g_crop,

	.vidioc_s_crop            = msm_jpegdma_s_crop,

	.vidioc_g_parm            = msm_jpegdma_g_parm,

	.vidioc_s_parm            = msm_jpegdma_s_parm,

};

/*

	plane_idx = ctx->plane_idx;

	config_idx = ctx->config_idx;

	msm_jpegdma_hw_start(ctx->jdma_device, &addr,

		&ctx->plane_config[config_idx].plane[plane_idx]);

		&ctx->plane_config[config_idx].plane[plane_idx],

		&ctx->plane_config[config_idx].speed);

}

/*

	struct vb2_buffer *dst_buf;

	struct jpegdma_ctx *ctx = priv;

	dev_dbg(ctx->jdma_device->dev, "Jpeg v4l2 dma device run E\n");

	dst_buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);

	src_buf = v4l2_m2m_next_src_buf(ctx->m2m_ctx);

	if (src_buf == NULL || dst_buf == NULL) {

		msm_jpegdma_schedule_next_config(ctx);

		ctx->pending_config = 0;

	}

	msm_jpegdma_process_buffers(ctx, src_buf, dst_buf);

	dev_dbg(ctx->jdma_device->dev, "Jpeg v4l2 dma device run X\n");

}

/*

	struct msm_jpegdma_device *jpegdma;

	int ret;

	dev_dbg(&pdev->dev, "jpeg v4l2 DMA probed\n");

	/* Jpeg dma device struct */

	jpegdma = kzalloc(sizeof(struct msm_jpegdma_device), GFP_KERNEL);

	if (!jpegdma)

	platform_set_drvdata(pdev, jpegdma);

	dev_dbg(&pdev->dev, "jpeg v4l2 DMA probe success\n");

	return 0;

error_video_register:

/* Max number of clocks defined in device tree */

#define MSM_JPEGDMA_MAX_CLK 10

/* Max number of clock rates defined in device tree */

#define MSM_JPEGDMA_MAX_CLK_RATES 5

/* Core clock index */

#define MSM_JPEGDMA_CORE_CLK 0

/* Max number of regulators defined in device tree */

#define MSM_JPEGDMA_MAX_REGULATOR_NUM 3

/* Max number of planes supported */

#define MSM_JPEGDMA_MAX_PIPES 2

/* Max number of hw configurations supported */

#define MSM_JPEGDMA_MAX_CONFIGS 2

/* Dma default fps */

#define MSM_JPEGDMA_DEFAULT_FPS 30

/* Dma input output size limitations */

#define MSM_JPEGDMA_MAX_WIDTH 65536

/*

 * struct msm_jpegdma_format - Dma format.

 * @name: Fomrat name.

 * @fourcc: v4l2 fourcc code

 * @name: Format name.

 * @fourcc: v4l2 fourcc code.

 * @depth: Number of bits per pixel.

 * @num_planes: number of planes.

 * @colplane_h: Color plane horizontal subsample.

 * @colplane_v: Color plane vertical subsample.

struct msm_jpegdma_format {

	char *name;

	u32 fourcc;

	int depth;

	int num_planes;

	int colplane_h;

	int colplane_v;

 * @left: Left position

 * @width: Width

 * @height: height.

 * @real_height: real height used to calculate plane offset.

 * @scanline: Number of lines per plane.

 * @stride: Stride bytes per line.

 */

struct msm_jpegdma_size {

	unsigned int left;

	unsigned int width;

	unsigned int height;

	unsigned int real_height;

	unsigned int scanline;

	unsigned int stride;

};

 * @in_size: Input size.

 * @out_size: Output size.

 * @format: Format.

 * @fps: Requested frames per second.

 */

struct msm_jpegdma_size_config {

	struct msm_jpegdma_size in_size;

	struct msm_jpegdma_size out_size;

	struct msm_jpegdma_format format;

	unsigned int fps;

};

/*

 * @block: Block settings.

 * @blocks_per_row: Blocks per row.

 * @blocks_per_col: Blocks per column.

 * @h_step: Horizontal setp value

 * @h_step: Horizontal step value

 * @v_step: Vertical step value

 * @h_step_last: Last horizontal step.

 * @v_step_last: Last vertical step.

	unsigned int out_offset;

};

/*

 * struct msm_jpegdma_plane_config - Contain input output address.

 * @bus_ab: Bus average bandwidth.

 * @bus_ib: Bus instantaneous bandwidth.

 * @core_clock: Core clock freq.

 */

struct msm_jpegdma_speed {

	u64 bus_ab;

	u64 bus_ib;

	u64 core_clock;

};

/*

 * struct msm_jpegdma_plane_config - Contain input output address.

 * @active_pipes: Number of active pipes.

 * struct msm_jpegdma_plane_config - Contain input output address.

 * @num_planes: Number of planes.

 * @plane: Plane configuration.

 * @speed: Processing speed.

 */

struct msm_jpegdma_plane_config {

	unsigned int num_planes;

	struct msm_jpegdma_plane plane[MSM_JPEGDMA_MAX_PLANES];

	struct msm_jpegdma_speed speed;

};

/*

/*

 * @jpegdma_ctx - Structure contains per open file handle context.

 * @lock: Lock protecting dma ctx.

 * @jdma_device: Pointer to fd device.

 * @jdma_device: Pointer to dma device.

 * @active: Set if context is active.

 * @completion: Context processing completion.

 * @fh: V4l2 file handle.

 * @format_cap: Current capture format.

 * @format_out: Current output format.

 * @crop: Current crop.

 * @timeperframe: Time per frame in seconds.

 * @config_idx: Plane configuration active index.

 * @plane_config: Array of plane configurations.

 * @pending_config: Flag set if there is pending plane configuration.

 * @plane_idx: Processing plane index.

 * @format_idx: Current format index.

 * @speed: Current speed value.

 */

struct jpegdma_ctx {

	struct mutex lock;

	struct v4l2_format format_cap;

	struct v4l2_format format_out;

	struct v4l2_rect crop;

	struct v4l2_fract timeperframe;

	unsigned int config_idx;

	struct msm_jpegdma_plane_config plane_config[MSM_JPEGDMA_MAX_CONFIGS];

	unsigned int plane_idx;

	unsigned int format_idx;

	unsigned int speed;

};

/*

 * @vdd: Pointer to vdd regulator.

 * @regulator_num: Number of regulators attached to the device.

 * @clk_num: Number of clocks attached to the device.

 * @clk: Array of clock resources used by fd device.

 * @clk_rates_num: Number of available clock rates.

 * @clk_rates: Array of clock rates set.

 * @clk: Array of clock resources used by dma device.

 * @clk_rates: Array of clock rates.

 * @vbif_regs_num: number of vbif  regs.

 * @vbif_regs: Array of vbif regs need to be set.

 * @qos_regs_num: Number of qos regs .

 * @hw_num_pipes: Number of dma hw pipes.

 * @active_clock_rate: Active clock rate index.

 * @hw_reset_completion: Dma reset completion.

 * @hw_halt_completion: Dma halt competion.

 * @hw_halt_completion: Dma halt completion.

 */

struct msm_jpegdma_device {

	struct mutex lock;

	unsigned int clk_num;

	struct clk *clk[MSM_JPEGDMA_MAX_CLK];

	unsigned int clk_rates_num;

	unsigned int clk_rates[MSM_JPEGDMA_MAX_CLK_RATES][MSM_JPEGDMA_MAX_CLK];

	unsigned int clk_rates[MSM_JPEGDMA_MAX_CLK];

	unsigned int vbif_regs_num;

	struct jpegdma_reg_cfg *vbif_regs;

	struct v4l2_m2m_dev *m2m_dev;

	int hw_num_pipes;

	int active_clock_rate;

	struct completion hw_reset_completion;

	struct completion hw_halt_completion;

	u64 active_clock_rate;

};

void msm_jpegdma_isr_processing_done(struct msm_jpegdma_device *dma);

int msm_jpegdma_hw_start(struct msm_jpegdma_device *dma,

	struct msm_jpegdma_addr *addr,

	struct msm_jpegdma_plane *plane);

	struct msm_jpegdma_plane *plane,

	struct msm_jpegdma_speed *speed);

int msm_jpegdma_hw_abort(struct msm_jpegdma_device *dma);

int msm_jpegdma_hw_update_bus_data(struct msm_jpegdma_device *dma,

	unsigned int clk_idx);

	u64 ab, u64 ib);

int msm_jpegdma_hw_handle_irq(struct msm_jpegdma_device *dma);

void msm_jpegdma_hw_put_vbif(struct msm_jpegdma_device *dma);

int msm_jpegdma_hw_update_clock_rate_idx(struct msm_jpegdma_device *dma,

	int clock_rate_idx);

int msm_jpegdma_hw_get_capabilities(struct msm_jpegdma_device *dma);

int msm_jpegdma_hw_get(struct msm_jpegdma_device *dma,

	unsigned int clock_rate_idx);

int msm_jpegdma_hw_get(struct msm_jpegdma_device *dma);

void msm_jpegdma_hw_put(struct msm_jpegdma_device *dma);