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Commit df72ddb6 authored by Pushkar Joshi's avatar Pushkar Joshi Committed by Matt Wagantall
Browse files

clk: msm: clock-mmss-8996: Support parent switching for display clocks 



The byte and pixel RCG clocks can have multiple parents. Use the new clk
ops which support switching between those parents. Update the frequency
table for those RCGs to list out all possible parents and add the missing
ones to the clock list.

Change-Id: I1d3148993c9813c8294f3f55a01e506198a8f1fd
Signed-off-by: default avatarPushkar Joshi <pushkarj@codeaurora.org>
parent 50a2a146

drivers/clk/msm/clock-mmss-8996.c

+75 −6
Original line number Diff line number Diff line
@@ -47,6 +47,7 @@ static void __iomem *virt_base_gpu; 
#define mmsscc_gpll0_mm_source_val		5

#define mmsscc_gpll0_div_mm_source_val		6

#define dsi0phypll_mm_source_val		1

#define dsi1phypll_mm_source_val		2

#define ext_extpclk_clk_src_mm_source_val	1

#define edp_mainlink_clk_src_mm_source_val	4

#define edp_pixel_clk_src_mm_source_val		5
@@ -815,47 +816,77 @@ static struct rcg_clk mdp_clk_src = { 
};



DEFINE_EXT_CLK(ext_pclk0_clk_src, NULL);

DEFINE_EXT_CLK(ext_pclk1_clk_src, NULL);

static struct clk_freq_tbl ftbl_pclk0_clk_src[] = {

	{

		.div_src_val = BVAL(10, 8, mmsscc_xo_mm_source_val)

				| BVAL(4, 0, 0),

		.src_clk = &mmsscc_xo.c,

		.freq_hz = 0,

	},

	{

		.div_src_val = BVAL(10, 8, dsi0phypll_mm_source_val)

				| BVAL(4, 0, 0),

		.src_clk = &ext_pclk0_clk_src.c,

		.freq_hz = 0,

	},

	{

		.div_src_val = BVAL(10, 8, dsi1phypll_mm_source_val)

				| BVAL(4, 0, 0),

		.src_clk = &ext_pclk1_clk_src.c,

		.freq_hz = 0,

	},

	F_END

};



static struct rcg_clk pclk0_clk_src = {

	.cmd_rcgr_reg = MMSS_PCLK0_CMD_RCGR,

	.set_rate = set_rate_mnd,

	.current_freq = ftbl_pclk0_clk_src,

	.freq_tbl = ftbl_pclk0_clk_src,

	.base = &virt_base,

	.c = {

		.dbg_name = "pclk0_clk_src",

		.parent = &ext_pclk0_clk_src.c,

		.ops = &clk_ops_pixel,

		.ops = &clk_ops_pixel_multiparent,

		VDD_DIG_FMAX_MAP3(LOWER, 175000000, LOW, 280000000,

							NOMINAL, 350000000),

		CLK_INIT(pclk0_clk_src.c),

	},

};



DEFINE_EXT_CLK(ext_pclk1_clk_src, NULL);

static struct clk_freq_tbl ftbl_pclk1_clk_src[] = {

	{

		.div_src_val = BVAL(10, 8, mmsscc_xo_mm_source_val)

				| BVAL(4, 0, 0),

		.src_clk = &mmsscc_xo.c,

		.freq_hz = 0,

	},

	{

		.div_src_val = BVAL(10, 8, dsi0phypll_mm_source_val)

				| BVAL(4, 0, 0),

		.src_clk = &ext_pclk0_clk_src.c,

		.freq_hz = 0,

	},

	{

		.div_src_val = BVAL(10, 8, dsi1phypll_mm_source_val)

				| BVAL(4, 0, 0),

		.src_clk = &ext_pclk1_clk_src.c,

		.freq_hz = 0,

	},

	F_END

};



static struct rcg_clk pclk1_clk_src = {

	.cmd_rcgr_reg = MMSS_PCLK1_CMD_RCGR,

	.set_rate = set_rate_mnd,

	.current_freq = ftbl_pclk1_clk_src,

	.freq_tbl = ftbl_pclk1_clk_src,

	.base = &virt_base,

	.c = {

		.dbg_name = "pclk1_clk_src",

		.parent = &ext_pclk1_clk_src.c,

		.ops = &clk_ops_pixel,

		.ops = &clk_ops_pixel_multiparent,

		VDD_DIG_FMAX_MAP3(LOWER, 175000000, LOW, 280000000,

							NOMINAL, 350000000),

		CLK_INIT(pclk1_clk_src.c),
@@ -1276,45 +1307,75 @@ static struct rcg_clk rbbmtimer_clk_src = { 
};



DEFINE_EXT_CLK(ext_byte0_clk_src, NULL);

DEFINE_EXT_CLK(ext_byte1_clk_src, NULL);

static struct clk_freq_tbl ftbl_byte0_clk_src[] = {

	{

		.div_src_val = BVAL(10, 8, mmsscc_xo_mm_source_val)

				| BVAL(4, 0, 0),

		.src_clk = &mmsscc_xo.c,

		.freq_hz = 0,

	},

	{

		.div_src_val = BVAL(10, 8, dsi0phypll_mm_source_val),

		.src_clk = &ext_byte0_clk_src.c,

		.freq_hz = 0,

	},

	{

		.div_src_val = BVAL(10, 8, dsi1phypll_mm_source_val)

				| BVAL(4, 0, 0),

		.src_clk = &ext_byte1_clk_src.c,

		.freq_hz = 0,

	},

	F_END

};



static struct rcg_clk byte0_clk_src = {

	.cmd_rcgr_reg = MMSS_BYTE0_CMD_RCGR,

	.set_rate = set_rate_hid,

	.current_freq = ftbl_byte0_clk_src,

	.freq_tbl = ftbl_byte0_clk_src,

	.base = &virt_base,

	.c = {

		.dbg_name = "byte0_clk_src",

		.parent = &ext_byte0_clk_src.c,

		.ops = &clk_ops_byte,

		.ops = &clk_ops_byte_multiparent,

		VDD_DIG_FMAX_MAP3(LOWER, 131250000, LOW, 210000000,

							NOMINAL, 262500000),

		CLK_INIT(byte0_clk_src.c),

	},

};



DEFINE_EXT_CLK(ext_byte1_clk_src, NULL);

static struct clk_freq_tbl ftbl_byte1_clk_src[] = {

	{

		.div_src_val = BVAL(10, 8, mmsscc_xo_mm_source_val)

				| BVAL(4, 0, 0),

		.src_clk = &mmsscc_xo.c,

		.freq_hz = 0,

	},

	{

		.div_src_val = BVAL(10, 8, dsi0phypll_mm_source_val),

		.src_clk = &ext_byte0_clk_src.c,

		.freq_hz = 0,

	},

	{

		.div_src_val = BVAL(10, 8, dsi1phypll_mm_source_val)

				| BVAL(4, 0, 0),

		.src_clk = &ext_byte1_clk_src.c,

		.freq_hz = 0,

	},

	F_END

};



static struct rcg_clk byte1_clk_src = {

	.cmd_rcgr_reg = MMSS_BYTE1_CMD_RCGR,

	.set_rate = set_rate_hid,

	.current_freq = ftbl_byte1_clk_src,

	.freq_tbl = ftbl_byte1_clk_src,

	.base = &virt_base,

	.c = {

		.dbg_name = "byte1_clk_src",

		.parent = &ext_byte1_clk_src.c,

		.ops = &clk_ops_byte,

		.ops = &clk_ops_byte_multiparent,

		VDD_DIG_FMAX_MAP3(LOWER, 131250000, LOW, 210000000,

							NOMINAL, 262500000),

		CLK_INIT(byte1_clk_src.c),
@@ -3286,6 +3347,10 @@ static struct clk_lookup msm_clocks_mmss_8996[] = { 
	CLK_LIST(mdss_axi_clk),

	CLK_LIST(mdss_byte0_clk),

	CLK_LIST(mdss_byte1_clk),

	CLK_LIST(byte0_clk_src),

	CLK_LIST(byte1_clk_src),

	CLK_LIST(ext_byte0_clk_src),

	CLK_LIST(ext_byte1_clk_src),

	CLK_LIST(mdss_edpaux_clk),

	CLK_LIST(mdss_edpgtc_clk),

	CLK_LIST(mdss_edplink_clk),
@@ -3298,6 +3363,10 @@ static struct clk_lookup msm_clocks_mmss_8996[] = { 
	CLK_LIST(mdss_mdp_clk),

	CLK_LIST(mdss_pclk0_clk),

	CLK_LIST(mdss_pclk1_clk),

	CLK_LIST(pclk0_clk_src),

	CLK_LIST(pclk1_clk_src),

	CLK_LIST(ext_pclk0_clk_src),

	CLK_LIST(ext_pclk1_clk_src),

	CLK_LIST(mdss_vsync_clk),

	CLK_LIST(mmss_misc_ahb_clk),

	CLK_LIST(mmss_misc_cxo_clk),

include/dt-bindings/clock/msm-clocks-8996.h

+8 −0
Original line number Diff line number Diff line
@@ -481,6 +481,14 @@ 
#define clk_mmpll8_postdiv_clk		0xedf57882

#define clk_mmpll9_postdiv_clk		0x3064b618

#define clk_gfx3d_clk_src_v2		0x4210acb7

#define clk_byte0_clk_src		0x75cc885b

#define clk_byte1_clk_src		0x63c2c955

#define clk_pclk0_clk_src		0xccac1f35

#define clk_pclk1_clk_src		0x090f68ac

#define clk_ext_byte0_clk_src		0xfb32f31e

#define clk_ext_byte1_clk_src		0x585ef6d4

#define clk_ext_pclk0_clk_src		0x087c1612

#define clk_ext_pclk1_clk_src		0x8067c5a3



/* clock_debug controlled clocks */

#define clk_gcc_debug_mux		0x8121ac15