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Commit de0024b6 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/sfr/next-fixes 

Pull powerpc fixes from Stephen Rothwell:
 "Three regresions in the PowerPC code.  One from v3.7 the others from
  this merge window."

* tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/sfr/next-fixes:
  powerpc: add a missing label in resume_kernel
  powerpc: Fix audit crash due to save/restore PPR changes
  powerpc: fix compiling CONFIG_PPC_TRANSACTIONAL_MEM when CONFIG_ALTIVEC=n
parents c208278c d8b92292

arch/powerpc/kernel/entry_64.S

+2 −2
Original line number Diff line number Diff line
@@ -304,7 +304,7 @@ syscall_exit_work: 
	subi	r12,r12,TI_FLAGS



4:	/* Anything else left to do? */

	SET_DEFAULT_THREAD_PPR(r3, r9)		/* Set thread.ppr = 3 */

	SET_DEFAULT_THREAD_PPR(r3, r10)		/* Set thread.ppr = 3 */

	andi.	r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP)

	beq	.ret_from_except_lite
@@ -657,7 +657,7 @@ resume_kernel: 
	/* Clear _TIF_EMULATE_STACK_STORE flag */

	lis	r11,_TIF_EMULATE_STACK_STORE@h

	addi	r5,r9,TI_FLAGS

	ldarx	r4,0,r5

0:	ldarx	r4,0,r5

	andc	r4,r4,r11

	stdcx.	r4,0,r5

	bne-	0b

arch/powerpc/kernel/process.c

+2 −0
Original line number Diff line number Diff line
@@ -555,10 +555,12 @@ static inline void tm_recheckpoint_new_task(struct task_struct *new) 
		new->thread.regs->msr |=

			(MSR_FP | new->thread.fpexc_mode);

	}

#ifdef CONFIG_ALTIVEC

	if (msr & MSR_VEC) {

		do_load_up_transact_altivec(&new->thread);

		new->thread.regs->msr |= MSR_VEC;

	}

#endif

	/* We may as well turn on VSX too since all the state is restored now */

	if (msr & MSR_VSX)

		new->thread.regs->msr |= MSR_VSX;

arch/powerpc/kernel/signal_32.c

+2 −0
Original line number Diff line number Diff line
@@ -866,10 +866,12 @@ static long restore_tm_user_regs(struct pt_regs *regs, 
		do_load_up_transact_fpu(&current->thread);

		regs->msr |= (MSR_FP | current->thread.fpexc_mode);

	}

#ifdef CONFIG_ALTIVEC

	if (msr & MSR_VEC) {

		do_load_up_transact_altivec(&current->thread);

		regs->msr |= MSR_VEC;

	}

#endif



	return 0;

}

arch/powerpc/kernel/signal_64.c

+2 −0
Original line number Diff line number Diff line
@@ -522,10 +522,12 @@ static long restore_tm_sigcontexts(struct pt_regs *regs, 
		do_load_up_transact_fpu(&current->thread);

		regs->msr |= (MSR_FP | current->thread.fpexc_mode);

	}

#ifdef CONFIG_ALTIVEC

	if (msr & MSR_VEC) {

		do_load_up_transact_altivec(&current->thread);

		regs->msr |= MSR_VEC;

	}

#endif



	return err;

}

arch/powerpc/kernel/tm.S

+2 −0
Original line number Diff line number Diff line
@@ -309,6 +309,7 @@ _GLOBAL(tm_recheckpoint) 
	or	r5, r6, r5			/* Set MSR.FP+.VSX/.VEC */

	mtmsr	r5



#ifdef CONFIG_ALTIVEC

	/* FP and VEC registers:  These are recheckpointed from thread.fpr[]

	 * and thread.vr[] respectively.  The thread.transact_fpr[] version

	 * is more modern, and will be loaded subsequently by any FPUnavailable
@@ -323,6 +324,7 @@ _GLOBAL(tm_recheckpoint) 
	REST_32VRS(0, r5, r3)			/* r5 scratch, r3 THREAD ptr */

	ld	r5, THREAD_VRSAVE(r3)

	mtspr	SPRN_VRSAVE, r5

#endif



dont_restore_vec:

	andi.	r0, r4, MSR_FP