crypto: ice: Add more ICE debug registers (dd3e2452) · Commits · e / devices / android_kernel_xiaomi_markw

drivers/crypto/msm/ice.c

+149 −9

Original line number	Original line	Diff line number	Diff line
	@@ -102,6 +102,8 @@ struct ice_device {
	struct regulator *reg;		struct regulator *reg;
	bool is_regulator_available;		bool is_regulator_available;
	struct qcom_ice_bus_vote bus_vote;		struct qcom_ice_bus_vote bus_vote;
			ktime_t ice_reset_start_time;
			ktime_t ice_reset_complete_time;
	};		};

	static int qti_ice_setting_config(struct request *req,		static int qti_ice_setting_config(struct request *req,
	@@ -1179,6 +1181,8 @@ static void qcom_ice_finish_power_collapse(void *data, async_cookie_t cookie)
	ice_dev->is_clear_irq_pending = false;		ice_dev->is_clear_irq_pending = false;
	}		}

			ice_dev->ice_reset_complete_time = ktime_get();

	if (ice_dev->success_cb && ice_dev->host_controller_data)		if (ice_dev->success_cb && ice_dev->host_controller_data)
	ice_dev->success_cb(ice_dev->host_controller_data,		ice_dev->success_cb(ice_dev->host_controller_data,
	ICE_RESUME_COMPLETION);		ICE_RESUME_COMPLETION);
	@@ -1221,6 +1225,47 @@ static int qcom_ice_resume(struct platform_device *pdev)
	}		}
	EXPORT_SYMBOL(qcom_ice_resume);		EXPORT_SYMBOL(qcom_ice_resume);

			static void qcom_ice_dump_test_bus(struct ice_device *ice_dev)
			{
			u32 reg = 0x1;
			u32 val;
			u8 bus_selector;
			u8 stream_selector;

			pr_err("ICE TEST BUS DUMP:\n");

			for (bus_selector = 0; bus_selector <= 0xF; bus_selector++) {
			reg = 0x1; /* enable test bus */
			reg \|= bus_selector << 28;
			if (bus_selector == 0xD)
			continue;
			qcom_ice_writel(ice_dev, reg, QCOM_ICE_REGS_TEST_BUS_CONTROL);
			/*
			* make sure test bus selector is written before reading
			* the test bus register
			*/
			mb();
			val = qcom_ice_readl(ice_dev, QCOM_ICE_REGS_TEST_BUS_REG);
			pr_err("ICE_TEST_BUS_CONTROL: 0x%08x \| ICE_TEST_BUS_REG: 0x%08x\n",
			reg, val);
			}

			pr_err("ICE TEST BUS DUMP (ICE_STREAM1_DATAPATH_TEST_BUS):\n");
			for (stream_selector = 0; stream_selector <= 0xF; stream_selector++) {
			reg = 0xD0000001; /* enable stream test bus */
			reg \|= stream_selector << 16;
			qcom_ice_writel(ice_dev, reg, QCOM_ICE_REGS_TEST_BUS_CONTROL);
			/*
			* make sure test bus selector is written before reading
			* the test bus register
			*/
			mb();
			val = qcom_ice_readl(ice_dev, QCOM_ICE_REGS_TEST_BUS_REG);
			pr_err("ICE_TEST_BUS_CONTROL: 0x%08x \| ICE_TEST_BUS_REG: 0x%08x\n",
			reg, val);
			}
			}

	static void qcom_ice_debug(struct platform_device *pdev)		static void qcom_ice_debug(struct platform_device *pdev)
	{		{
	struct ice_device *ice_dev;		struct ice_device *ice_dev;
	@@ -1236,35 +1281,35 @@ static void qcom_ice_debug(struct platform_device *pdev)
	if (!ice_dev->is_ice_enabled)		if (!ice_dev->is_ice_enabled)
	pr_err("%s: ICE device is not enabled\n", __func__);		pr_err("%s: ICE device is not enabled\n", __func__);

	pr_info("%s: =========== REGISTER DUMP (%p)===========\n",		pr_err("%s: =========== REGISTER DUMP (%p)===========\n",
	ice_dev->ice_instance_type, ice_dev);		ice_dev->ice_instance_type, ice_dev);

	pr_info("%s: ICE Control: 0x%08x \| ICE Reset: 0x%08x\n",		pr_err("%s: ICE Control: 0x%08x \| ICE Reset: 0x%08x\n",
	ice_dev->ice_instance_type,		ice_dev->ice_instance_type,
	qcom_ice_readl(ice_dev, QCOM_ICE_REGS_CONTROL),		qcom_ice_readl(ice_dev, QCOM_ICE_REGS_CONTROL),
	qcom_ice_readl(ice_dev, QCOM_ICE_REGS_RESET));		qcom_ice_readl(ice_dev, QCOM_ICE_REGS_RESET));

	pr_info("%s: ICE Version: 0x%08x \| ICE FUSE: 0x%08x\n",		pr_err("%s: ICE Version: 0x%08x \| ICE FUSE: 0x%08x\n",
	ice_dev->ice_instance_type,		ice_dev->ice_instance_type,
	qcom_ice_readl(ice_dev, QCOM_ICE_REGS_VERSION),		qcom_ice_readl(ice_dev, QCOM_ICE_REGS_VERSION),
	qcom_ice_readl(ice_dev, QCOM_ICE_REGS_FUSE_SETTING));		qcom_ice_readl(ice_dev, QCOM_ICE_REGS_FUSE_SETTING));

	pr_info("%s: ICE Param1: 0x%08x \| ICE Param2: 0x%08x\n",		pr_err("%s: ICE Param1: 0x%08x \| ICE Param2: 0x%08x\n",
	ice_dev->ice_instance_type,		ice_dev->ice_instance_type,
	qcom_ice_readl(ice_dev, QCOM_ICE_REGS_PARAMETERS_1),		qcom_ice_readl(ice_dev, QCOM_ICE_REGS_PARAMETERS_1),
	qcom_ice_readl(ice_dev, QCOM_ICE_REGS_PARAMETERS_2));		qcom_ice_readl(ice_dev, QCOM_ICE_REGS_PARAMETERS_2));

	pr_info("%s: ICE Param3: 0x%08x \| ICE Param4: 0x%08x\n",		pr_err("%s: ICE Param3: 0x%08x \| ICE Param4: 0x%08x\n",
	ice_dev->ice_instance_type,		ice_dev->ice_instance_type,
	qcom_ice_readl(ice_dev, QCOM_ICE_REGS_PARAMETERS_3),		qcom_ice_readl(ice_dev, QCOM_ICE_REGS_PARAMETERS_3),
	qcom_ice_readl(ice_dev, QCOM_ICE_REGS_PARAMETERS_4));		qcom_ice_readl(ice_dev, QCOM_ICE_REGS_PARAMETERS_4));

	pr_info("%s: ICE Param5: 0x%08x \| ICE IRQ STTS: 0x%08x\n",		pr_err("%s: ICE Param5: 0x%08x \| ICE IRQ STTS: 0x%08x\n",
	ice_dev->ice_instance_type,		ice_dev->ice_instance_type,
	qcom_ice_readl(ice_dev, QCOM_ICE_REGS_PARAMETERS_5),		qcom_ice_readl(ice_dev, QCOM_ICE_REGS_PARAMETERS_5),
	qcom_ice_readl(ice_dev, QCOM_ICE_REGS_NON_SEC_IRQ_STTS));		qcom_ice_readl(ice_dev, QCOM_ICE_REGS_NON_SEC_IRQ_STTS));

	pr_info("%s: ICE IRQ MASK: 0x%08x \| ICE IRQ CLR: 0x%08x\n",		pr_err("%s: ICE IRQ MASK: 0x%08x \| ICE IRQ CLR: 0x%08x\n",
	ice_dev->ice_instance_type,		ice_dev->ice_instance_type,
	qcom_ice_readl(ice_dev, QCOM_ICE_REGS_NON_SEC_IRQ_MASK),		qcom_ice_readl(ice_dev, QCOM_ICE_REGS_NON_SEC_IRQ_MASK),
	qcom_ice_readl(ice_dev, QCOM_ICE_REGS_NON_SEC_IRQ_CLR));		qcom_ice_readl(ice_dev, QCOM_ICE_REGS_NON_SEC_IRQ_CLR));
	@@ -1272,17 +1317,110 @@ static void qcom_ice_debug(struct platform_device *pdev)
	if ((ICE_REV(ice_dev->ice_hw_version, MAJOR) > 2) \|\|		if ((ICE_REV(ice_dev->ice_hw_version, MAJOR) > 2) \|\|
	((ICE_REV(ice_dev->ice_hw_version, MAJOR) == 2) &&		((ICE_REV(ice_dev->ice_hw_version, MAJOR) == 2) &&
	(ICE_REV(ice_dev->ice_hw_version, MINOR) >= 1))) {		(ICE_REV(ice_dev->ice_hw_version, MINOR) >= 1))) {
	pr_info("%s: ICE BIST Sts: 0x%08x \| ICE Bypass Sts: 0x%08x\n",		pr_err("%s: ICE BIST Sts: 0x%08x \| ICE Bypass Sts: 0x%08x\n",
	ice_dev->ice_instance_type,		ice_dev->ice_instance_type,
	qcom_ice_readl(ice_dev, QCOM_ICE_REGS_BIST_STATUS),		qcom_ice_readl(ice_dev, QCOM_ICE_REGS_BIST_STATUS),
	qcom_ice_readl(ice_dev, QCOM_ICE_REGS_BYPASS_STATUS));		qcom_ice_readl(ice_dev, QCOM_ICE_REGS_BYPASS_STATUS));
	}		}

	pr_info("%s: ICE ADV CTRL: 0x%08x \| ICE ENDIAN SWAP: 0x%08x\n",		pr_err("%s: ICE ADV CTRL: 0x%08x \| ICE ENDIAN SWAP: 0x%08x\n",
	ice_dev->ice_instance_type,		ice_dev->ice_instance_type,
	qcom_ice_readl(ice_dev, QCOM_ICE_REGS_ADVANCED_CONTROL),		qcom_ice_readl(ice_dev, QCOM_ICE_REGS_ADVANCED_CONTROL),
	qcom_ice_readl(ice_dev, QCOM_ICE_REGS_ENDIAN_SWAP));		qcom_ice_readl(ice_dev, QCOM_ICE_REGS_ENDIAN_SWAP));

			pr_err("%s: ICE_STM1_ERR_SYND1: 0x%08x \| ICE_STM1_ERR_SYND2: 0x%08x\n",
			ice_dev->ice_instance_type,
			qcom_ice_readl(ice_dev, QCOM_ICE_REGS_STREAM1_ERROR_SYNDROME1),
			qcom_ice_readl(ice_dev, QCOM_ICE_REGS_STREAM1_ERROR_SYNDROME2));

			pr_err("%s: ICE_STM2_ERR_SYND1: 0x%08x \| ICE_STM2_ERR_SYND2: 0x%08x\n",
			ice_dev->ice_instance_type,
			qcom_ice_readl(ice_dev, QCOM_ICE_REGS_STREAM2_ERROR_SYNDROME1),
			qcom_ice_readl(ice_dev, QCOM_ICE_REGS_STREAM2_ERROR_SYNDROME2));

			pr_err("%s: ICE_STM1_COUNTER1: 0x%08x \| ICE_STM1_COUNTER2: 0x%08x\n",
			ice_dev->ice_instance_type,
			qcom_ice_readl(ice_dev, QCOM_ICE_REGS_STREAM1_COUNTERS1),
			qcom_ice_readl(ice_dev, QCOM_ICE_REGS_STREAM1_COUNTERS2));

			pr_err("%s: ICE_STM1_COUNTER3: 0x%08x \| ICE_STM1_COUNTER4: 0x%08x\n",
			ice_dev->ice_instance_type,
			qcom_ice_readl(ice_dev, QCOM_ICE_REGS_STREAM1_COUNTERS3),
			qcom_ice_readl(ice_dev, QCOM_ICE_REGS_STREAM1_COUNTERS4));

			pr_err("%s: ICE_STM2_COUNTER1: 0x%08x \| ICE_STM2_COUNTER2: 0x%08x\n",
			ice_dev->ice_instance_type,
			qcom_ice_readl(ice_dev, QCOM_ICE_REGS_STREAM2_COUNTERS1),
			qcom_ice_readl(ice_dev, QCOM_ICE_REGS_STREAM2_COUNTERS2));

			pr_err("%s: ICE_STM2_COUNTER3: 0x%08x \| ICE_STM2_COUNTER4: 0x%08x\n",
			ice_dev->ice_instance_type,
			qcom_ice_readl(ice_dev, QCOM_ICE_REGS_STREAM2_COUNTERS3),
			qcom_ice_readl(ice_dev, QCOM_ICE_REGS_STREAM2_COUNTERS4));

			pr_err("%s: ICE_STM1_CTR5_MSB: 0x%08x \| ICE_STM1_CTR5_LSB: 0x%08x\n",
			ice_dev->ice_instance_type,
			qcom_ice_readl(ice_dev, QCOM_ICE_REGS_STREAM1_COUNTERS5_MSB),
			qcom_ice_readl(ice_dev, QCOM_ICE_REGS_STREAM1_COUNTERS5_LSB));

			pr_err("%s: ICE_STM1_CTR6_MSB: 0x%08x \| ICE_STM1_CTR6_LSB: 0x%08x\n",
			ice_dev->ice_instance_type,
			qcom_ice_readl(ice_dev, QCOM_ICE_REGS_STREAM1_COUNTERS6_MSB),
			qcom_ice_readl(ice_dev, QCOM_ICE_REGS_STREAM1_COUNTERS6_LSB));

			pr_err("%s: ICE_STM1_CTR7_MSB: 0x%08x \| ICE_STM1_CTR7_LSB: 0x%08x\n",
			ice_dev->ice_instance_type,
			qcom_ice_readl(ice_dev, QCOM_ICE_REGS_STREAM1_COUNTERS7_MSB),
			qcom_ice_readl(ice_dev, QCOM_ICE_REGS_STREAM1_COUNTERS7_LSB));

			pr_err("%s: ICE_STM1_CTR8_MSB: 0x%08x \| ICE_STM1_CTR8_LSB: 0x%08x\n",
			ice_dev->ice_instance_type,
			qcom_ice_readl(ice_dev, QCOM_ICE_REGS_STREAM1_COUNTERS8_MSB),
			qcom_ice_readl(ice_dev, QCOM_ICE_REGS_STREAM1_COUNTERS8_LSB));

			pr_err("%s: ICE_STM1_CTR9_MSB: 0x%08x \| ICE_STM1_CTR9_LSB: 0x%08x\n",
			ice_dev->ice_instance_type,
			qcom_ice_readl(ice_dev, QCOM_ICE_REGS_STREAM1_COUNTERS9_MSB),
			qcom_ice_readl(ice_dev, QCOM_ICE_REGS_STREAM1_COUNTERS9_LSB));

			pr_err("%s: ICE_STM2_CTR5_MSB: 0x%08x \| ICE_STM2_CTR5_LSB: 0x%08x\n",
			ice_dev->ice_instance_type,
			qcom_ice_readl(ice_dev, QCOM_ICE_REGS_STREAM2_COUNTERS5_MSB),
			qcom_ice_readl(ice_dev, QCOM_ICE_REGS_STREAM2_COUNTERS5_LSB));

			pr_err("%s: ICE_STM2_CTR6_MSB: 0x%08x \| ICE_STM2_CTR6_LSB: 0x%08x\n",
			ice_dev->ice_instance_type,
			qcom_ice_readl(ice_dev, QCOM_ICE_REGS_STREAM2_COUNTERS6_MSB),
			qcom_ice_readl(ice_dev, QCOM_ICE_REGS_STREAM2_COUNTERS6_LSB));

			pr_err("%s: ICE_STM2_CTR7_MSB: 0x%08x \| ICE_STM2_CTR7_LSB: 0x%08x\n",
			ice_dev->ice_instance_type,
			qcom_ice_readl(ice_dev, QCOM_ICE_REGS_STREAM2_COUNTERS7_MSB),
			qcom_ice_readl(ice_dev, QCOM_ICE_REGS_STREAM2_COUNTERS7_LSB));

			pr_err("%s: ICE_STM2_CTR8_MSB: 0x%08x \| ICE_STM2_CTR8_LSB: 0x%08x\n",
			ice_dev->ice_instance_type,
			qcom_ice_readl(ice_dev, QCOM_ICE_REGS_STREAM2_COUNTERS8_MSB),
			qcom_ice_readl(ice_dev, QCOM_ICE_REGS_STREAM2_COUNTERS8_LSB));

			pr_err("%s: ICE_STM2_CTR9_MSB: 0x%08x \| ICE_STM2_CTR9_LSB: 0x%08x\n",
			ice_dev->ice_instance_type,
			qcom_ice_readl(ice_dev, QCOM_ICE_REGS_STREAM2_COUNTERS9_MSB),
			qcom_ice_readl(ice_dev, QCOM_ICE_REGS_STREAM2_COUNTERS9_LSB));

			qcom_ice_dump_test_bus(ice_dev);
			pr_err("%s: ICE reset start time: %u ICE reset done time: %u\n",
			ice_dev->ice_instance_type,
			(unsigned int)ice_dev->ice_reset_start_time.tv64,
			(unsigned int)ice_dev->ice_reset_complete_time.tv64);

			if (ktime_to_us(ktime_sub(ice_dev->ice_reset_complete_time,
			ice_dev->ice_reset_start_time)) > 0)
			pr_err("%s: Time taken for reset: %lu\n",
			ice_dev->ice_instance_type,
			(unsigned long)ktime_to_us(ktime_sub(
			ice_dev->ice_reset_complete_time,
			ice_dev->ice_reset_start_time)));
	}		}
	EXPORT_SYMBOL(qcom_ice_debug);		EXPORT_SYMBOL(qcom_ice_debug);

	@@ -1297,6 +1435,8 @@ static int qcom_ice_reset(struct platform_device *pdev)
	return -EINVAL;		return -EINVAL;
	}		}

			ice_dev->ice_reset_start_time = ktime_get();

	async_schedule(qcom_ice_finish_power_collapse, ice_dev);		async_schedule(qcom_ice_finish_power_collapse, ice_dev);
	return 0;		return 0;
	}		}

drivers/crypto/msm/iceregs.h

+8 −0

Original line number	Original line	Diff line number	Diff line
	@@ -41,6 +41,14 @@
	#define QCOM_ICE_REGS_NON_SEC_IRQ_STTS 0x0040		#define QCOM_ICE_REGS_NON_SEC_IRQ_STTS 0x0040
	#define QCOM_ICE_REGS_NON_SEC_IRQ_MASK 0x0044		#define QCOM_ICE_REGS_NON_SEC_IRQ_MASK 0x0044
	#define QCOM_ICE_REGS_NON_SEC_IRQ_CLR 0x0048		#define QCOM_ICE_REGS_NON_SEC_IRQ_CLR 0x0048
			#define QCOM_ICE_REGS_STREAM1_ERROR_SYNDROME1 0x0050
			#define QCOM_ICE_REGS_STREAM1_ERROR_SYNDROME2 0x0054
			#define QCOM_ICE_REGS_STREAM2_ERROR_SYNDROME1 0x0058
			#define QCOM_ICE_REGS_STREAM2_ERROR_SYNDROME2 0x005C
			#define QCOM_ICE_REGS_STREAM1_BIST_ERROR_VEC 0x0060
			#define QCOM_ICE_REGS_STREAM2_BIST_ERROR_VEC 0x0064
			#define QCOM_ICE_REGS_STREAM1_BIST_FINISH_VEC 0x0068
			#define QCOM_ICE_REGS_STREAM2_BIST_FINISH_VEC 0x006C
	#define QCOM_ICE_REGS_BIST_STATUS 0x0070		#define QCOM_ICE_REGS_BIST_STATUS 0x0070
	#define QCOM_ICE_REGS_BYPASS_STATUS 0x0074		#define QCOM_ICE_REGS_BYPASS_STATUS 0x0074
	#define QCOM_ICE_REGS_ADVANCED_CONTROL 0x1000		#define QCOM_ICE_REGS_ADVANCED_CONTROL 0x1000