Merge branch 'for_3_2/omap_misc' of git://gitorious.org/omap-sw-develoment/linux-omap-dev into l3 (dc9ca24f) · Commits · e / devices / android_kernel_xiaomi_markw

arch/arm/mach-omap2/omap_l3_noc.c

+67 −63

Original line number	Original line	Diff line number	Diff line
	@@ -56,11 +56,11 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
	{		{

	struct omap4_l3 *l3 = _l3;		struct omap4_l3 *l3 = _l3;
	int inttype, i, j;		int inttype, i, k;
	int err_src = 0;		int err_src = 0;
	u32 std_err_main_addr, std_err_main, err_reg;		u32 std_err_main, err_reg, clear, masterid;
	u32 base, slave_addr, clear;		void __iomem base, l3_targ_base;
	char *source_name;		char target_name, master_name = "UN IDENTIFIED";

	/* Get the Type of interrupt */		/* Get the Type of interrupt */
	inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;		inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
	@@ -70,43 +70,50 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
	* Read the regerr register of the clock domain		* Read the regerr register of the clock domain
	* to determine the source		* to determine the source
	*/		*/
	base = (u32)l3->l3_base[i];		base = l3->l3_base[i];
	err_reg = readl(base + l3_flagmux[i] + (inttype << 3));		err_reg = __raw_readl(base + l3_flagmux[i] +
			+ L3_FLAGMUX_REGERR0 + (inttype << 3));

	/* Get the corresponding error and analyse */		/* Get the corresponding error and analyse */
	if (err_reg) {		if (err_reg) {
	/* Identify the source from control status register */		/* Identify the source from control status register */
	for (j = 0; !(err_reg & (1 << j)); j++)		err_src = __ffs(err_reg);
	;

	err_src = j;
	/* Read the stderrlog_main_source from clk domain */		/* Read the stderrlog_main_source from clk domain */
	std_err_main_addr = base + *(l3_targ[i] + err_src);		l3_targ_base = base + *(l3_targ[i] + err_src);
	std_err_main = readl(std_err_main_addr);		std_err_main = __raw_readl(l3_targ_base +
			L3_TARG_STDERRLOG_MAIN);
			masterid = __raw_readl(l3_targ_base +
			L3_TARG_STDERRLOG_MSTADDR);

	switch (std_err_main & CUSTOM_ERROR) {		switch (std_err_main & CUSTOM_ERROR) {
	case STANDARD_ERROR:		case STANDARD_ERROR:
	source_name =		target_name =
	l3_targ_stderrlog_main_name[i][err_src];		l3_targ_inst_name[i][err_src];
			WARN(true, "L3 standard error: TARGET:%s at address 0x%x\n",
	slave_addr = std_err_main_addr +		target_name,
	L3_SLAVE_ADDRESS_OFFSET;		__raw_readl(l3_targ_base +
	WARN(true, "L3 standard error: SOURCE:%s at address 0x%x\n",		L3_TARG_STDERRLOG_SLVOFSLSB));
	source_name, readl(slave_addr));
	/* clear the std error log*/		/* clear the std error log*/
	clear = std_err_main \| CLEAR_STDERR_LOG;		clear = std_err_main \| CLEAR_STDERR_LOG;
	writel(clear, std_err_main_addr);		writel(clear, l3_targ_base +
			L3_TARG_STDERRLOG_MAIN);
	break;		break;

	case CUSTOM_ERROR:		case CUSTOM_ERROR:
	source_name =		target_name =
	l3_targ_stderrlog_main_name[i][err_src];		l3_targ_inst_name[i][err_src];
			for (k = 0; k < NUM_OF_L3_MASTERS; k++) {
	WARN(true, "CUSTOM SRESP error with SOURCE:%s\n",		if (masterid == l3_masters[k].id)
	source_name);		master_name =
			l3_masters[k].name;
			}
			WARN(true, "L3 custom error: MASTER:%s TARGET:%s\n",
			master_name, target_name);
	/* clear the std error log*/		/* clear the std error log*/
	clear = std_err_main \| CLEAR_STDERR_LOG;		clear = std_err_main \| CLEAR_STDERR_LOG;
	writel(clear, std_err_main_addr);		writel(clear, l3_targ_base +
			L3_TARG_STDERRLOG_MAIN);
	break;		break;

	default:		default:
	@@ -125,7 +132,6 @@ static int __init omap4_l3_probe(struct platform_device *pdev)
	static struct omap4_l3 *l3;		static struct omap4_l3 *l3;
	struct resource *res;		struct resource *res;
	int ret;		int ret;
	int irq;

	l3 = kzalloc(sizeof(*l3), GFP_KERNEL);		l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
	if (!l3)		if (!l3)
	@@ -177,8 +183,8 @@ static int __init omap4_l3_probe(struct platform_device *pdev)
	/*		/*
	* Setup interrupt Handlers		* Setup interrupt Handlers
	*/		*/
	irq = platform_get_irq(pdev, 0);		l3->debug_irq = platform_get_irq(pdev, 0);
	ret = request_irq(irq,		ret = request_irq(l3->debug_irq,
	l3_interrupt_handler,		l3_interrupt_handler,
	IRQF_DISABLED, "l3-dbg-irq", l3);		IRQF_DISABLED, "l3-dbg-irq", l3);
	if (ret) {		if (ret) {
	@@ -186,10 +192,9 @@ static int __init omap4_l3_probe(struct platform_device *pdev)
	OMAP44XX_IRQ_L3_DBG);		OMAP44XX_IRQ_L3_DBG);
	goto err3;		goto err3;
	}		}
	l3->debug_irq = irq;

	irq = platform_get_irq(pdev, 1);		l3->app_irq = platform_get_irq(pdev, 1);
	ret = request_irq(irq,		ret = request_irq(l3->app_irq,
	l3_interrupt_handler,		l3_interrupt_handler,
	IRQF_DISABLED, "l3-app-irq", l3);		IRQF_DISABLED, "l3-app-irq", l3);
	if (ret) {		if (ret) {
	@@ -197,7 +202,6 @@ static int __init omap4_l3_probe(struct platform_device *pdev)
	OMAP44XX_IRQ_L3_APP);		OMAP44XX_IRQ_L3_APP);
	goto err4;		goto err4;
	}		}
	l3->app_irq = irq;

	return 0;		return 0;

arch/arm/mach-omap2/omap_l3_noc.h

+127 −97

Original line number	Original line	Diff line number	Diff line
	@@ -23,63 +23,94 @@
	#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H		#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
	#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H		#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H

	/*
	* L3 register offsets
	*/
	#define L3_MODULES 3		#define L3_MODULES 3
	#define CLEAR_STDERR_LOG (1 << 31)		#define CLEAR_STDERR_LOG (1 << 31)
	#define CUSTOM_ERROR 0x2		#define CUSTOM_ERROR 0x2
	#define STANDARD_ERROR 0x0		#define STANDARD_ERROR 0x0
	#define INBAND_ERROR 0x0		#define INBAND_ERROR 0x0
	#define EMIF_KERRLOG_OFFSET 0x10
	#define L3_SLAVE_ADDRESS_OFFSET 0x14
	#define LOGICAL_ADDR_ERRORLOG 0x4
	#define L3_APPLICATION_ERROR 0x0		#define L3_APPLICATION_ERROR 0x0
	#define L3_DEBUG_ERROR 0x1		#define L3_DEBUG_ERROR 0x1

	u32 l3_flagmux[L3_MODULES] = {		/* L3 TARG register offsets */
	0x50C,		#define L3_TARG_STDERRLOG_MAIN 0x48
	0x100C,		#define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
	0X020C		#define L3_TARG_STDERRLOG_MSTADDR 0x68
			#define L3_FLAGMUX_REGERR0 0xc

			#define NUM_OF_L3_MASTERS (sizeof(l3_masters)/sizeof(l3_masters[0]))

			static u32 l3_flagmux[L3_MODULES] = {
			0x500,
			0x1000,
			0X0200
	};		};

	/*		/* L3 Target standard Error register offsets */
	* L3 Target standard Error register offsets		static u32 l3_targ_inst_clk1[] = {
	*/		0x100, /* DMM1 */
	u32 l3_targ_stderrlog_main_clk1[] = {		0x200, /* DMM2 */
	0x148, /* DMM1 */		0x300, /* ABE */
	0x248, /* DMM2 */		0x400, /* L4CFG */
	0x348, /* ABE */		0x600 /* CLK2 PWR DISC */
	0x448, /* L4CFG */		};
	0x648 /* CLK2 PWR DISC */
			static u32 l3_targ_inst_clk2[] = {
			0x500, /* CORTEX M3 */
			0x300, /* DSS */
			0x100, /* GPMC */
			0x400, /* ISS */
			0x700, /* IVAHD */
			0xD00, /* missing in TRM corresponds to AES1*/
			0x900, /* L4 PER0*/
			0x200, /* OCMRAM */
			0x100, /* missing in TRM corresponds to GPMC sERROR*/
			0x600, /* SGX */
			0x800, /* SL2 */
			0x1600, /* C2C */
			0x1100, /* missing in TRM corresponds PWR DISC CLK1*/
			0xF00, /* missing in TRM corrsponds to SHA1*/
			0xE00, /* missing in TRM corresponds to AES2*/
			0xC00, /* L4 PER3 */
			0xA00, /* L4 PER1*/
			0xB00 /* L4 PER2*/
	};		};

	u32 l3_targ_stderrlog_main_clk2[] = {		static u32 l3_targ_inst_clk3[] = {
	0x548, /* CORTEX M3 */		0x0100 /* EMUSS */
	0x348, /* DSS */
	0x148, /* GPMC */
	0x448, /* ISS */
	0x748, /* IVAHD */
	0xD48, /* missing in TRM corresponds to AES1*/
	0x948, /* L4 PER0*/
	0x248, /* OCMRAM */
	0x148, /* missing in TRM corresponds to GPMC sERROR*/
	0x648, /* SGX */
	0x848, /* SL2 */
	0x1648, /* C2C */
	0x1148, /* missing in TRM corresponds PWR DISC CLK1*/
	0xF48, /* missing in TRM corrsponds to SHA1*/
	0xE48, /* missing in TRM corresponds to AES2*/
	0xC48, /* L4 PER3 */
	0xA48, /* L4 PER1*/
	0xB48 /* L4 PER2*/
	};		};

	u32 l3_targ_stderrlog_main_clk3[] = {		static struct l3_masters_data {
	0x0148 /* EMUSS */		u32 id;
			char name[10];
			} l3_masters[] = {
			{ 0x0 , "MPU"},
			{ 0x10, "CS_ADP"},
			{ 0x14, "xxx"},
			{ 0x20, "DSP"},
			{ 0x30, "IVAHD"},
			{ 0x40, "ISS"},
			{ 0x44, "DucatiM3"},
			{ 0x48, "FaceDetect"},
			{ 0x50, "SDMA_Rd"},
			{ 0x54, "SDMA_Wr"},
			{ 0x58, "xxx"},
			{ 0x5C, "xxx"},
			{ 0x60, "SGX"},
			{ 0x70, "DSS"},
			{ 0x80, "C2C"},
			{ 0x88, "xxx"},
			{ 0x8C, "xxx"},
			{ 0x90, "HSI"},
			{ 0xA0, "MMC1"},
			{ 0xA4, "MMC2"},
			{ 0xA8, "MMC6"},
			{ 0xB0, "UNIPRO1"},
			{ 0xC0, "USBHOSTHS"},
			{ 0xC4, "USBOTGHS"},
			{ 0xC8, "USBHOSTFS"}
	};		};

	char *l3_targ_stderrlog_main_name[L3_MODULES][18] = {		static char *l3_targ_inst_name[L3_MODULES][18] = {
	{		{
	"DMM1",		"DMM1",
	"DMM2",		"DMM2",
	@@ -112,10 +143,10 @@ char *l3_targ_stderrlog_main_name[L3_MODULES][18] = {
	},		},
	};		};

	u32 *l3_targ[L3_MODULES] = {		static u32 *l3_targ[L3_MODULES] = {
	l3_targ_stderrlog_main_clk1,		l3_targ_inst_clk1,
	l3_targ_stderrlog_main_clk2,		l3_targ_inst_clk2,
	l3_targ_stderrlog_main_clk3,		l3_targ_inst_clk3,
	};		};

	struct omap4_l3 {		struct omap4_l3 {
	@@ -123,10 +154,9 @@ struct omap4_l3 {
	struct clk *ick;		struct clk *ick;

	/* memory base */		/* memory base */
	void __iomem *l3_base[4];		void __iomem *l3_base[L3_MODULES];

	int debug_irq;		int debug_irq;
	int app_irq;		int app_irq;
	};		};

	#endif		#endif

arch/arm/mach-omap2/omap_l3_smx.c

+44 −47

Original line number	Original line	Diff line number	Diff line
	@@ -135,7 +135,7 @@ static char *omap3_l3_initiator_string(u8 initid)
	}		}
	}		}

	/**		/*
	* omap3_l3_block_irq - handles a register block's irq		* omap3_l3_block_irq - handles a register block's irq
	* @l3: struct omap3_l3 *		* @l3: struct omap3_l3 *
	* @base: register block base address		* @base: register block base address
	@@ -158,8 +158,7 @@ static irqreturn_t omap3_l3_block_irq(struct omap3_l3 *l3,
	WARN(true, "%s seen by %s %s at address %x\n",		WARN(true, "%s seen by %s %s at address %x\n",
	omap3_l3_code_string(code),		omap3_l3_code_string(code),
	omap3_l3_initiator_string(initid),		omap3_l3_initiator_string(initid),
	multi ? "Multiple Errors" : "",		multi ? "Multiple Errors" : "", address);
	address);

	return IRQ_HANDLED;		return IRQ_HANDLED;
	}		}
	@@ -191,14 +190,12 @@ static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
	}		}

	/* identify the error source */		/* identify the error source */
	for (err_source = 0; !(status & (1 << err_source)); err_source++)		err_source = __ffs(status);
	;

	base = l3->rt + *(omap3_l3_bases[int_type] + err_source);		base = l3->rt + omap3_l3_bases[int_type][err_source];
	error = omap3_l3_readll(base, L3_ERROR_LOG);		error = omap3_l3_readll(base, L3_ERROR_LOG);
	if (error) {		if (error) {
	error_addr = omap3_l3_readll(base, L3_ERROR_LOG_ADDR);		error_addr = omap3_l3_readll(base, L3_ERROR_LOG_ADDR);

	ret \|= omap3_l3_block_irq(l3, error, error_addr);		ret \|= omap3_l3_block_irq(l3, error, error_addr);
	}		}

arch/arm/mach-omap2/omap_l3_smx.h

+82 −82

Original line number	Original line	Diff line number	Diff line
	@@ -40,7 +40,7 @@
	#define L3_SI_CONTROL 0x020		#define L3_SI_CONTROL 0x020
	#define L3_SI_FLAG_STATUS_0 0x510		#define L3_SI_FLAG_STATUS_0 0x510

	const u64 shift = 1;		static const u64 shift = 1;

	#define L3_STATUS_0_MPUIA_BRST (shift << 0)		#define L3_STATUS_0_MPUIA_BRST (shift << 0)
	#define L3_STATUS_0_MPUIA_RSP (shift << 1)		#define L3_STATUS_0_MPUIA_RSP (shift << 1)
	@@ -206,7 +206,7 @@ struct omap3_l3 {
	};		};

	/* offsets for l3 agents in order with the Flag status register */		/* offsets for l3 agents in order with the Flag status register */
	unsigned int __iomem omap3_l3_app_bases[] = {		static unsigned int omap3_l3_app_bases[] = {
	/* MPU IA */		/* MPU IA */
	0x1400,		0x1400,
	0x1400,		0x1400,
	@@ -305,7 +305,7 @@ unsigned int __iomem omap3_l3_app_bases[] = {
	0,		0,
	};		};

	unsigned int __iomem omap3_l3_debug_bases[] = {		static unsigned int omap3_l3_debug_bases[] = {
	/* MPU DATA IA */		/* MPU DATA IA */
	0x1400,		0x1400,
	/* RESERVED */		/* RESERVED */
	@@ -321,7 +321,7 @@ unsigned int __iomem omap3_l3_debug_bases[] = {
	/* REST RESERVED */		/* REST RESERVED */
	};		};

	u32 *omap3_l3_bases[] = {		static u32 *omap3_l3_bases[] = {
	omap3_l3_app_bases,		omap3_l3_app_bases,
	omap3_l3_debug_bases,		omap3_l3_debug_bases,
	};		};

arch/arm/plat-omap/include/plat/io.h

+2 −2

Original line number	Original line	Diff line number	Diff line
	@@ -228,13 +228,13 @@

	#define OMAP44XX_EMIF2_PHYS OMAP44XX_EMIF2_BASE		#define OMAP44XX_EMIF2_PHYS OMAP44XX_EMIF2_BASE
	/* 0x4d000000 --> 0xfd200000 */		/* 0x4d000000 --> 0xfd200000 */
	#define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF2_PHYS + OMAP4_L3_PER_IO_OFFSET)
	#define OMAP44XX_EMIF2_SIZE SZ_1M		#define OMAP44XX_EMIF2_SIZE SZ_1M
			#define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF1_VIRT + OMAP44XX_EMIF1_SIZE)

	#define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE		#define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE
	/* 0x4e000000 --> 0xfd300000 */		/* 0x4e000000 --> 0xfd300000 */
	#define OMAP44XX_DMM_VIRT (OMAP44XX_DMM_PHYS + OMAP4_L3_PER_IO_OFFSET)
	#define OMAP44XX_DMM_SIZE SZ_1M		#define OMAP44XX_DMM_SIZE SZ_1M
			#define OMAP44XX_DMM_VIRT (OMAP44XX_EMIF2_VIRT + OMAP44XX_EMIF2_SIZE)
	/*		/*
	* ----------------------------------------------------------------------------		* ----------------------------------------------------------------------------
	* Omap specific register access		* Omap specific register access