Loading drivers/gpu/drm/nouveau/core/include/subdev/vm.h +1 −0 Original line number Diff line number Diff line Loading @@ -69,6 +69,7 @@ struct nouveau_vmmgr { struct nouveau_subdev base; u64 limit; u8 dma_bits; u32 pgt_bits; u8 spg_shift; u8 lpg_shift; Loading drivers/gpu/drm/nouveau/core/subdev/vm/nv04.c +1 −0 Original line number Diff line number Diff line Loading @@ -97,6 +97,7 @@ nv04_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, priv->base.create = nv04_vm_create; priv->base.limit = NV04_PDMA_SIZE; priv->base.dma_bits = 32; priv->base.pgt_bits = 32 - 12; priv->base.spg_shift = 12; priv->base.lpg_shift = 12; Loading drivers/gpu/drm/nouveau/core/subdev/vm/nv41.c +1 −0 Original line number Diff line number Diff line Loading @@ -98,6 +98,7 @@ nv41_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, priv->base.create = nv04_vm_create; priv->base.limit = NV41_GART_SIZE; priv->base.dma_bits = 39; priv->base.pgt_bits = 32 - 12; priv->base.spg_shift = 12; priv->base.lpg_shift = 12; Loading drivers/gpu/drm/nouveau/core/subdev/vm/nv44.c +1 −0 Original line number Diff line number Diff line Loading @@ -179,6 +179,7 @@ nv44_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, priv->base.create = nv04_vm_create; priv->base.limit = NV44_GART_SIZE; priv->base.dma_bits = 39; priv->base.pgt_bits = 32 - 12; priv->base.spg_shift = 12; priv->base.lpg_shift = 12; Loading drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c +1 −0 Original line number Diff line number Diff line Loading @@ -201,6 +201,7 @@ nv50_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return ret; priv->base.limit = 1ULL << 40; priv->base.dma_bits = 40; priv->base.pgt_bits = 29 - 12; priv->base.spg_shift = 12; priv->base.lpg_shift = 16; Loading Loading
drivers/gpu/drm/nouveau/core/include/subdev/vm.h +1 −0 Original line number Diff line number Diff line Loading @@ -69,6 +69,7 @@ struct nouveau_vmmgr { struct nouveau_subdev base; u64 limit; u8 dma_bits; u32 pgt_bits; u8 spg_shift; u8 lpg_shift; Loading
drivers/gpu/drm/nouveau/core/subdev/vm/nv04.c +1 −0 Original line number Diff line number Diff line Loading @@ -97,6 +97,7 @@ nv04_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, priv->base.create = nv04_vm_create; priv->base.limit = NV04_PDMA_SIZE; priv->base.dma_bits = 32; priv->base.pgt_bits = 32 - 12; priv->base.spg_shift = 12; priv->base.lpg_shift = 12; Loading
drivers/gpu/drm/nouveau/core/subdev/vm/nv41.c +1 −0 Original line number Diff line number Diff line Loading @@ -98,6 +98,7 @@ nv41_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, priv->base.create = nv04_vm_create; priv->base.limit = NV41_GART_SIZE; priv->base.dma_bits = 39; priv->base.pgt_bits = 32 - 12; priv->base.spg_shift = 12; priv->base.lpg_shift = 12; Loading
drivers/gpu/drm/nouveau/core/subdev/vm/nv44.c +1 −0 Original line number Diff line number Diff line Loading @@ -179,6 +179,7 @@ nv44_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, priv->base.create = nv04_vm_create; priv->base.limit = NV44_GART_SIZE; priv->base.dma_bits = 39; priv->base.pgt_bits = 32 - 12; priv->base.spg_shift = 12; priv->base.lpg_shift = 12; Loading
drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c +1 −0 Original line number Diff line number Diff line Loading @@ -201,6 +201,7 @@ nv50_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return ret; priv->base.limit = 1ULL << 40; priv->base.dma_bits = 40; priv->base.pgt_bits = 29 - 12; priv->base.spg_shift = 12; priv->base.lpg_shift = 16; Loading