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Commit dc468e3d authored by Amitkumar Karwar's avatar Amitkumar Karwar Committed by John W. Linville
Browse files

mwifiex: remove unnecessary macros in sdio.h 



They are not used in the code.

Signed-off-by: default avatarAmitkumar Karwar <akarwar@marvell.com>
Signed-off-by: default avatarBing Zhao <bzhao@marvell.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 248eb4c6

drivers/net/wireless/mwifiex/sdio.h

+0 −51
Original line number Diff line number Diff line
@@ -66,14 +66,8 @@ 


/* Host Control Registers : Configuration */

#define CONFIGURATION_REG		0x00

/* Host Control Registers : Host without Command 53 finish host*/

#define HOST_TO_CARD_EVENT       (0x1U << 3)

/* Host Control Registers : Host without Command 53 finish host */

#define HOST_WO_CMD53_FINISH_HOST	(0x1U << 2)

/* Host Control Registers : Host power up */

#define HOST_POWER_UP			(0x1U << 1)

/* Host Control Registers : Host power down */

#define HOST_POWER_DOWN			(0x1U << 0)



/* Host Control Registers : Host interrupt mask */

#define HOST_INT_MASK_REG		0x02
@@ -93,60 +87,15 @@ 


/* Host Control Registers : Host interrupt RSR */

#define HOST_INT_RSR_REG		0x01

/* Host Control Registers : Upload host interrupt RSR */

#define UP_LD_HOST_INT_RSR		(0x1U)



/* Host Control Registers : Host interrupt status */

#define HOST_INT_STATUS_REG		0x28

/* Host Control Registers : Upload CRC error */

#define UP_LD_CRC_ERR			(0x1U << 2)

/* Host Control Registers : Upload restart */

#define UP_LD_RESTART                   (0x1U << 1)

/* Host Control Registers : Download restart */

#define DN_LD_RESTART                   (0x1U << 0)



/* Card Control Registers : Card I/O ready */

#define CARD_IO_READY                   (0x1U << 3)

/* Card Control Registers : CIS card ready */

#define CIS_CARD_RDY                    (0x1U << 2)

/* Card Control Registers : Upload card ready */

#define UP_LD_CARD_RDY                  (0x1U << 1)

/* Card Control Registers : Download card ready */

#define DN_LD_CARD_RDY                  (0x1U << 0)



/* Card Control Registers : Host interrupt mask register */

#define HOST_INTERRUPT_MASK_REG         0x34

/* Card Control Registers : Host power interrupt mask */

#define HOST_POWER_INT_MASK             (0x1U << 3)

/* Card Control Registers : Abort card interrupt mask */

#define ABORT_CARD_INT_MASK             (0x1U << 2)

/* Card Control Registers : Upload card interrupt mask */

#define UP_LD_CARD_INT_MASK             (0x1U << 1)

/* Card Control Registers : Download card interrupt mask */

#define DN_LD_CARD_INT_MASK             (0x1U << 0)



/* Card Control Registers : Card interrupt status register */

#define CARD_INTERRUPT_STATUS_REG       0x38

/* Card Control Registers : Power up interrupt */

#define POWER_UP_INT                    (0x1U << 4)

/* Card Control Registers : Power down interrupt */

#define POWER_DOWN_INT                  (0x1U << 3)



/* Card Control Registers : Card interrupt RSR register */

#define CARD_INTERRUPT_RSR_REG          0x3c

/* Card Control Registers : Power up RSR */

#define POWER_UP_RSR                    (0x1U << 4)

/* Card Control Registers : Power down RSR */

#define POWER_DOWN_RSR                  (0x1U << 3)



/* Host F1 card ready */

#define HOST_F1_CARD_RDY		0x0020



/* Rx length register */

#define CARD_RX_LEN_REG			0x62

/* Rx unit register */

#define CARD_RX_UNIT_REG		0x63



/* Max retry number of CMD53 write */

#define MAX_WRITE_IOMEM_RETRY		2