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Commit dc34b05f authored by Douglas Leung's avatar Douglas Leung Committed by Ralf Baechle
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MIPS: Fix decoding of c0_config1 for MIPSxx caches with 32 ways per set. 



This affects certain 4Kc cores.

Signed-off-by: default avatarDouglas Leung <douglas@mips.com>
Signed-off-by: default avatarSteven J. Hill <sjhill@mips.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3855/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent c0226306

arch/mips/mm/c-r4k.c

+2 −2
Original line number Diff line number Diff line
@@ -977,7 +977,7 @@ static void __cpuinit probe_pcache(void) 
			c->icache.linesz = 2 << lsize;

		else

			c->icache.linesz = lsize;

		c->icache.sets = 64 << ((config1 >> 22) & 7);

		c->icache.sets = 32 << (((config1 >> 22) + 1) & 7);

		c->icache.ways = 1 + ((config1 >> 16) & 7);



		icache_size = c->icache.sets *
@@ -997,7 +997,7 @@ static void __cpuinit probe_pcache(void) 
			c->dcache.linesz = 2 << lsize;

		else

			c->dcache.linesz= lsize;

		c->dcache.sets = 64 << ((config1 >> 13) & 7);

		c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7);

		c->dcache.ways = 1 + ((config1 >> 7) & 7);



		dcache_size = c->dcache.sets *