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Commit db8c0286 authored by Loc Ho's avatar Loc Ho Committed by Tejun Heo
Browse files

arm64: Add APM X-Gene SoC AHCI SATA host controller DTS entries 



This patch adds APM X-Gene SoC AHCI SATA host controller DTS entries.

Signed-off-by: default avatarLoc Ho <lho@apm.com>
Signed-off-by: default avatarTuan Phan <tphan@apm.com>
Signed-off-by: default avatarSuman Tripathi <stripathi@apm.com>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarTejun Heo <tj@kernel.org>
parent 81d01bfa

arch/arm64/boot/dts/apm-storm.dtsi

+80 −0
Original line number Diff line number Diff line
@@ -218,6 +218,45 @@ 
				enable-offset = <0x0>;

				enable-mask = <0x06>;

			};



			sata01clk: sata01clk@1f21c000 {

				compatible = "apm,xgene-device-clock";

				#clock-cells = <1>;

				clocks = <&socplldiv2 0>;

				reg = <0x0 0x1f21c000 0x0 0x1000>;

				reg-names = "csr-reg";

				clock-output-names = "sata01clk";

				csr-offset = <0x4>;

				csr-mask = <0x05>;

				enable-offset = <0x0>;

				enable-mask = <0x39>;

			};



			sata23clk: sata23clk@1f22c000 {

				compatible = "apm,xgene-device-clock";

				#clock-cells = <1>;

				clocks = <&socplldiv2 0>;

				reg = <0x0 0x1f22c000 0x0 0x1000>;

				reg-names = "csr-reg";

				clock-output-names = "sata23clk";

				csr-offset = <0x4>;

				csr-mask = <0x05>;

				enable-offset = <0x0>;

				enable-mask = <0x39>;

			};



			sata45clk: sata45clk@1f23c000 {

				compatible = "apm,xgene-device-clock";

				#clock-cells = <1>;

				clocks = <&socplldiv2 0>;

				reg = <0x0 0x1f23c000 0x0 0x1000>;

				reg-names = "csr-reg";

				clock-output-names = "sata45clk";

				csr-offset = <0x4>;

				csr-mask = <0x05>;

				enable-offset = <0x0>;

				enable-mask = <0x39>;

			};

		};



		serial0: serial@1c020000 {
@@ -259,5 +298,46 @@ 
			apm,tx-boost-gain = <31 31 31 31 31 31>;

			apm,tx-eye-tuning = <2 10 10 2 10 10>;

		};



		sata1: sata@1a000000 {

			compatible = "apm,xgene-ahci";

			reg = <0x0 0x1a000000 0x0 0x1000>,

			      <0x0 0x1f210000 0x0 0x1000>,

			      <0x0 0x1f21d000 0x0 0x1000>,

			      <0x0 0x1f21e000 0x0 0x1000>,

			      <0x0 0x1f217000 0x0 0x1000>;

			interrupts = <0x0 0x86 0x4>;

			status = "disabled";

			clocks = <&sata01clk 0>;

			phys = <&phy1 0>;

			phy-names = "sata-phy";

		};



		sata2: sata@1a400000 {

			compatible = "apm,xgene-ahci";

			reg = <0x0 0x1a400000 0x0 0x1000>,

			      <0x0 0x1f220000 0x0 0x1000>,

			      <0x0 0x1f22d000 0x0 0x1000>,

			      <0x0 0x1f22e000 0x0 0x1000>,

			      <0x0 0x1f227000 0x0 0x1000>;

			interrupts = <0x0 0x87 0x4>;

			status = "ok";

			clocks = <&sata23clk 0>;

			phys = <&phy2 0>;

			phy-names = "sata-phy";

		};



		sata3: sata@1a800000 {

			compatible = "apm,xgene-ahci";

			reg = <0x0 0x1a800000 0x0 0x1000>,

			      <0x0 0x1f230000 0x0 0x1000>,

			      <0x0 0x1f23d000 0x0 0x1000>,

			      <0x0 0x1f23e000 0x0 0x1000>;

			interrupts = <0x0 0x88 0x4>;

			status = "ok";

			clocks = <&sata45clk 0>;

			phys = <&phy3 0>;

			phy-names = "sata-phy";

		};

	};

};