Loading drivers/gpu/msm/adreno.c +2 −1 Original line number Diff line number Diff line Loading @@ -89,7 +89,8 @@ static struct adreno_device device_3d0 = { .long_ib_detect = 1, .input_work = __WORK_INITIALIZER(device_3d0.input_work, adreno_input_work), .pwrctrl_flag = BIT(ADRENO_SPTP_PC_CTRL) | BIT(ADRENO_PPD_CTRL), .pwrctrl_flag = BIT(ADRENO_SPTP_PC_CTRL) | BIT(ADRENO_PPD_CTRL) | BIT(ADRENO_LM_CTRL), .profile.enabled = false, }; Loading drivers/gpu/msm/adreno_a5xx.c +2 −2 Original line number Diff line number Diff line Loading @@ -1384,8 +1384,8 @@ static void a5xx_lm_init(struct adreno_device *adreno_dev) kgsl_regwrite(device, A5XX_GPMU_BASE_LEAKAGE, gfx_base_leakage(adreno_dev)); /* default of 6A */ kgsl_regwrite(device, A5XX_GPMU_GPMU_PWR_THRESHOLD, 0x80001000); /* Enable the power threshold and set it to 6000m */ kgsl_regwrite(device, A5XX_GPMU_GPMU_PWR_THRESHOLD, 0x80000000 | 6000); kgsl_regwrite(device, A5XX_GPMU_BEC_ENABLE, 0x10001FFF); kgsl_regwrite(device, A5XX_GDPM_CONFIG1, 0x00201FF1); Loading Loading
drivers/gpu/msm/adreno.c +2 −1 Original line number Diff line number Diff line Loading @@ -89,7 +89,8 @@ static struct adreno_device device_3d0 = { .long_ib_detect = 1, .input_work = __WORK_INITIALIZER(device_3d0.input_work, adreno_input_work), .pwrctrl_flag = BIT(ADRENO_SPTP_PC_CTRL) | BIT(ADRENO_PPD_CTRL), .pwrctrl_flag = BIT(ADRENO_SPTP_PC_CTRL) | BIT(ADRENO_PPD_CTRL) | BIT(ADRENO_LM_CTRL), .profile.enabled = false, }; Loading
drivers/gpu/msm/adreno_a5xx.c +2 −2 Original line number Diff line number Diff line Loading @@ -1384,8 +1384,8 @@ static void a5xx_lm_init(struct adreno_device *adreno_dev) kgsl_regwrite(device, A5XX_GPMU_BASE_LEAKAGE, gfx_base_leakage(adreno_dev)); /* default of 6A */ kgsl_regwrite(device, A5XX_GPMU_GPMU_PWR_THRESHOLD, 0x80001000); /* Enable the power threshold and set it to 6000m */ kgsl_regwrite(device, A5XX_GPMU_GPMU_PWR_THRESHOLD, 0x80000000 | 6000); kgsl_regwrite(device, A5XX_GPMU_BEC_ENABLE, 0x10001FFF); kgsl_regwrite(device, A5XX_GDPM_CONFIG1, 0x00201FF1); Loading