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Commit db086715 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "clk: msm: clock: Enable auto-calibration during certain LPM mode paths"

parents b23a0088 7b85f9aa

Documentation/devicetree/bindings/arm/msm/clock-cpu-8996.txt

+1 −1
Original line number Diff line number Diff line
@@ -7,7 +7,7 @@ PLL FMAXes etc. 


Required properties:

- compatible:		Must be either "qcom,cpu-clock-8996" or

			"qcom,cpu-clock-8996-v3"

			"qcom,cpu-clock-8996-v3" or "qcom,cpu-clock-8996-pro"

- reg:			Pairs of physical base addresses and region sizes of

			memory mapped registers.

- reg-names:		Names of the bases for the above registers. Expected

arch/arm/boot/dts/qcom/msm8996pro.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -527,7 +527,7 @@ 
};



&clock_cpu {

	compatible = "qcom,cpu-clock-8996-v3";

	compatible = "qcom,cpu-clock-8996-pro";

	qcom,pwrcl-speedbin0-v0 =

		<          0  0 >,

		<  307200000  1 >,

drivers/clk/msm/clock-cpu-8996.c

+30 −10
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.

 * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -66,6 +66,7 @@ static char *base_names[] = { 


static void *vbases[NUM_BASES];

static bool cpu_clocks_v3;

static bool cpu_clocks_pro;



static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner, NULL);
@@ -122,6 +123,8 @@ static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner, NULL); 
#define APC_DIAG_OFFSET	0x48

#define MUX_OFFSET	0x40



#define MDD_DROOP_CODE	0x7C



DEFINE_EXT_CLK(xo_ao, NULL);

DEFINE_CLK_DUMMY(alpha_xo_ao, 19200000);

DEFINE_EXT_CLK(sys_apcsaux_clk_gcc, NULL);
@@ -1424,6 +1427,7 @@ static int cpu_clock_8996_driver_probe(struct platform_device *pdev) 
static struct of_device_id match_table[] = {

	{ .compatible = "qcom,cpu-clock-8996" },

	{ .compatible = "qcom,cpu-clock-8996-v3" },

	{ .compatible = "qcom,cpu-clock-8996-pro" },

	{}

};
@@ -1500,16 +1504,16 @@ int __init cpu_clock_8996_early_init(void) 
	int ret = 0;

	void __iomem *auxbase;

	u32 regval;

	struct device_node *ofnode;



	ofnode = of_find_compatible_node(NULL, NULL,

					 "qcom,cpu-clock-8996-v3");

	if (ofnode)

	if (of_find_compatible_node(NULL, NULL,

					 "qcom,cpu-clock-8996-pro")) {

		cpu_clocks_v3 = true;

		cpu_clocks_pro = true;

	} else if (of_find_compatible_node(NULL, NULL,

					 "qcom,cpu-clock-8996-v3")) {

		cpu_clocks_v3 = true;

	else {

		ofnode = of_find_compatible_node(NULL, NULL,

					 "qcom,cpu-clock-8996");

		if (!ofnode)

	} else if (!of_find_compatible_node(NULL, NULL,

					 "qcom,cpu-clock-8996")) {

		return 0;

	}
@@ -1753,6 +1757,22 @@ int __init cpu_clock_8996_early_init(void) 
		perfcl_clk.has_acd = true;

		pwrcl_clk.has_acd = true;



		if (cpu_clocks_pro) {

			/*

			 * Configure ACS logic to switch to always-on clock

			 * source during D2-D5 entry

			 */

			writel_relaxed(0x2, vbases[APC0_BASE] +

							MDD_DROOP_CODE);

			writel_relaxed(0x2, vbases[APC1_BASE] +

							MDD_DROOP_CODE);

			/*

			 * Ensure that the writes go through before enabling

			 * ACD.

			 */

			wmb();

		}



		/* Enable ACD on this cluster if necessary */

		cpu_clock_8996_acd_init();