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Commit dade7716 authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

x86: Convert ioapic_lock and vector_lock to raw_spinlock 



Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent 9d133e5d

arch/x86/kernel/apic/io_apic.c

+53 −53
Original line number Diff line number Diff line
@@ -73,8 +73,8 @@ 
 */

int sis_apic_bug = -1;



static DEFINE_SPINLOCK(ioapic_lock);

static DEFINE_SPINLOCK(vector_lock);

static DEFINE_RAW_SPINLOCK(ioapic_lock);

static DEFINE_RAW_SPINLOCK(vector_lock);



/*

 * # of IRQ routing registers
@@ -393,7 +393,7 @@ static bool io_apic_level_ack_pending(struct irq_cfg *cfg) 
	struct irq_pin_list *entry;

	unsigned long flags;



	spin_lock_irqsave(&ioapic_lock, flags);

	raw_spin_lock_irqsave(&ioapic_lock, flags);

	for_each_irq_pin(entry, cfg->irq_2_pin) {

		unsigned int reg;

		int pin;
@@ -402,11 +402,11 @@ static bool io_apic_level_ack_pending(struct irq_cfg *cfg) 
		reg = io_apic_read(entry->apic, 0x10 + pin*2);

		/* Is the remote IRR bit set? */

		if (reg & IO_APIC_REDIR_REMOTE_IRR) {

			spin_unlock_irqrestore(&ioapic_lock, flags);

			raw_spin_unlock_irqrestore(&ioapic_lock, flags);

			return true;

		}

	}

	spin_unlock_irqrestore(&ioapic_lock, flags);

	raw_spin_unlock_irqrestore(&ioapic_lock, flags);



	return false;

}
@@ -420,10 +420,10 @@ static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) 
{

	union entry_union eu;

	unsigned long flags;

	spin_lock_irqsave(&ioapic_lock, flags);

	raw_spin_lock_irqsave(&ioapic_lock, flags);

	eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);

	eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);

	spin_unlock_irqrestore(&ioapic_lock, flags);

	raw_spin_unlock_irqrestore(&ioapic_lock, flags);

	return eu.entry;

}
@@ -446,9 +446,9 @@ __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) 
void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)

{

	unsigned long flags;

	spin_lock_irqsave(&ioapic_lock, flags);

	raw_spin_lock_irqsave(&ioapic_lock, flags);

	__ioapic_write_entry(apic, pin, e);

	spin_unlock_irqrestore(&ioapic_lock, flags);

	raw_spin_unlock_irqrestore(&ioapic_lock, flags);

}



/*
@@ -461,10 +461,10 @@ static void ioapic_mask_entry(int apic, int pin) 
	unsigned long flags;

	union entry_union eu = { .entry.mask = 1 };



	spin_lock_irqsave(&ioapic_lock, flags);

	raw_spin_lock_irqsave(&ioapic_lock, flags);

	io_apic_write(apic, 0x10 + 2*pin, eu.w1);

	io_apic_write(apic, 0x11 + 2*pin, eu.w2);

	spin_unlock_irqrestore(&ioapic_lock, flags);

	raw_spin_unlock_irqrestore(&ioapic_lock, flags);

}



/*
@@ -591,9 +591,9 @@ static void mask_IO_APIC_irq_desc(struct irq_desc *desc) 


	BUG_ON(!cfg);



	spin_lock_irqsave(&ioapic_lock, flags);

	raw_spin_lock_irqsave(&ioapic_lock, flags);

	__mask_IO_APIC_irq(cfg);

	spin_unlock_irqrestore(&ioapic_lock, flags);

	raw_spin_unlock_irqrestore(&ioapic_lock, flags);

}



static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
@@ -601,9 +601,9 @@ static void unmask_IO_APIC_irq_desc(struct irq_desc *desc) 
	struct irq_cfg *cfg = desc->chip_data;

	unsigned long flags;



	spin_lock_irqsave(&ioapic_lock, flags);

	raw_spin_lock_irqsave(&ioapic_lock, flags);

	__unmask_IO_APIC_irq(cfg);

	spin_unlock_irqrestore(&ioapic_lock, flags);

	raw_spin_unlock_irqrestore(&ioapic_lock, flags);

}



static void mask_IO_APIC_irq(unsigned int irq)
@@ -1127,12 +1127,12 @@ void lock_vector_lock(void) 
	/* Used to the online set of cpus does not change

	 * during assign_irq_vector.

	 */

	spin_lock(&vector_lock);

	raw_spin_lock(&vector_lock);

}



void unlock_vector_lock(void)

{

	spin_unlock(&vector_lock);

	raw_spin_unlock(&vector_lock);

}



static int
@@ -1220,9 +1220,9 @@ int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) 
	int err;

	unsigned long flags;



	spin_lock_irqsave(&vector_lock, flags);

	raw_spin_lock_irqsave(&vector_lock, flags);

	err = __assign_irq_vector(irq, cfg, mask);

	spin_unlock_irqrestore(&vector_lock, flags);

	raw_spin_unlock_irqrestore(&vector_lock, flags);

	return err;

}
@@ -1265,7 +1265,7 @@ void __setup_vector_irq(int cpu) 
	 * assignments that might be happening on another cpu in parallel,

	 * while we setup our initial vector to irq mappings.

	 */

	spin_lock(&vector_lock);

	raw_spin_lock(&vector_lock);

	/* Mark the inuse vectors */

	for_each_irq_desc(irq, desc) {

		cfg = desc->chip_data;
@@ -1284,7 +1284,7 @@ void __setup_vector_irq(int cpu) 
		if (!cpumask_test_cpu(cpu, cfg->domain))

			per_cpu(vector_irq, cpu)[vector] = -1;

	}

	spin_unlock(&vector_lock);

	raw_spin_unlock(&vector_lock);

}



static struct irq_chip ioapic_chip;
@@ -1603,14 +1603,14 @@ __apicdebuginit(void) print_IO_APIC(void) 


	for (apic = 0; apic < nr_ioapics; apic++) {



	spin_lock_irqsave(&ioapic_lock, flags);

	raw_spin_lock_irqsave(&ioapic_lock, flags);

	reg_00.raw = io_apic_read(apic, 0);

	reg_01.raw = io_apic_read(apic, 1);

	if (reg_01.bits.version >= 0x10)

		reg_02.raw = io_apic_read(apic, 2);

	if (reg_01.bits.version >= 0x20)

		reg_03.raw = io_apic_read(apic, 3);

	spin_unlock_irqrestore(&ioapic_lock, flags);

	raw_spin_unlock_irqrestore(&ioapic_lock, flags);



	printk("\n");

	printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
@@ -1905,9 +1905,9 @@ void __init enable_IO_APIC(void) 
	 * The number of IO-APIC IRQ registers (== #pins):

	 */

	for (apic = 0; apic < nr_ioapics; apic++) {

		spin_lock_irqsave(&ioapic_lock, flags);

		raw_spin_lock_irqsave(&ioapic_lock, flags);

		reg_01.raw = io_apic_read(apic, 1);

		spin_unlock_irqrestore(&ioapic_lock, flags);

		raw_spin_unlock_irqrestore(&ioapic_lock, flags);

		nr_ioapic_registers[apic] = reg_01.bits.entries+1;

	}
@@ -2047,9 +2047,9 @@ void __init setup_ioapic_ids_from_mpc(void) 
	for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {



		/* Read the register 0 value */

		spin_lock_irqsave(&ioapic_lock, flags);

		raw_spin_lock_irqsave(&ioapic_lock, flags);

		reg_00.raw = io_apic_read(apic_id, 0);

		spin_unlock_irqrestore(&ioapic_lock, flags);

		raw_spin_unlock_irqrestore(&ioapic_lock, flags);



		old_id = mp_ioapics[apic_id].apicid;
@@ -2108,16 +2108,16 @@ void __init setup_ioapic_ids_from_mpc(void) 
			mp_ioapics[apic_id].apicid);



		reg_00.bits.ID = mp_ioapics[apic_id].apicid;

		spin_lock_irqsave(&ioapic_lock, flags);

		raw_spin_lock_irqsave(&ioapic_lock, flags);

		io_apic_write(apic_id, 0, reg_00.raw);

		spin_unlock_irqrestore(&ioapic_lock, flags);

		raw_spin_unlock_irqrestore(&ioapic_lock, flags);



		/*

		 * Sanity check

		 */

		spin_lock_irqsave(&ioapic_lock, flags);

		raw_spin_lock_irqsave(&ioapic_lock, flags);

		reg_00.raw = io_apic_read(apic_id, 0);

		spin_unlock_irqrestore(&ioapic_lock, flags);

		raw_spin_unlock_irqrestore(&ioapic_lock, flags);

		if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)

			printk("could not set ID!\n");

		else
@@ -2200,7 +2200,7 @@ static unsigned int startup_ioapic_irq(unsigned int irq) 
	unsigned long flags;

	struct irq_cfg *cfg;



	spin_lock_irqsave(&ioapic_lock, flags);

	raw_spin_lock_irqsave(&ioapic_lock, flags);

	if (irq < nr_legacy_irqs) {

		disable_8259A_irq(irq);

		if (i8259A_irq_pending(irq))
@@ -2208,7 +2208,7 @@ static unsigned int startup_ioapic_irq(unsigned int irq) 
	}

	cfg = irq_cfg(irq);

	__unmask_IO_APIC_irq(cfg);

	spin_unlock_irqrestore(&ioapic_lock, flags);

	raw_spin_unlock_irqrestore(&ioapic_lock, flags);



	return was_pending;

}
@@ -2219,9 +2219,9 @@ static int ioapic_retrigger_irq(unsigned int irq) 
	struct irq_cfg *cfg = irq_cfg(irq);

	unsigned long flags;



	spin_lock_irqsave(&vector_lock, flags);

	raw_spin_lock_irqsave(&vector_lock, flags);

	apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);

	spin_unlock_irqrestore(&vector_lock, flags);

	raw_spin_unlock_irqrestore(&vector_lock, flags);



	return 1;

}
@@ -2314,14 +2314,14 @@ set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask) 
	irq = desc->irq;

	cfg = desc->chip_data;



	spin_lock_irqsave(&ioapic_lock, flags);

	raw_spin_lock_irqsave(&ioapic_lock, flags);

	ret = set_desc_affinity(desc, mask, &dest);

	if (!ret) {

		/* Only the high 8 bits are valid. */

		dest = SET_APIC_LOGICAL_ID(dest);

		__target_IO_APIC_irq(irq, dest, cfg);

	}

	spin_unlock_irqrestore(&ioapic_lock, flags);

	raw_spin_unlock_irqrestore(&ioapic_lock, flags);



	return ret;

}
@@ -2549,9 +2549,9 @@ static void eoi_ioapic_irq(struct irq_desc *desc) 
	irq = desc->irq;

	cfg = desc->chip_data;



	spin_lock_irqsave(&ioapic_lock, flags);

	raw_spin_lock_irqsave(&ioapic_lock, flags);

	__eoi_ioapic_irq(irq, cfg);

	spin_unlock_irqrestore(&ioapic_lock, flags);

	raw_spin_unlock_irqrestore(&ioapic_lock, flags);

}



static void ack_apic_level(unsigned int irq)
@@ -3133,13 +3133,13 @@ static int ioapic_resume(struct sys_device *dev) 
	data = container_of(dev, struct sysfs_ioapic_data, dev);

	entry = data->entry;



	spin_lock_irqsave(&ioapic_lock, flags);

	raw_spin_lock_irqsave(&ioapic_lock, flags);

	reg_00.raw = io_apic_read(dev->id, 0);

	if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {

		reg_00.bits.ID = mp_ioapics[dev->id].apicid;

		io_apic_write(dev->id, 0, reg_00.raw);

	}

	spin_unlock_irqrestore(&ioapic_lock, flags);

	raw_spin_unlock_irqrestore(&ioapic_lock, flags);

	for (i = 0; i < nr_ioapic_registers[dev->id]; i++)

		ioapic_write_entry(dev->id, i, entry[i]);
@@ -3202,7 +3202,7 @@ unsigned int create_irq_nr(unsigned int irq_want, int node) 
	if (irq_want < nr_irqs_gsi)

		irq_want = nr_irqs_gsi;



	spin_lock_irqsave(&vector_lock, flags);

	raw_spin_lock_irqsave(&vector_lock, flags);

	for (new = irq_want; new < nr_irqs; new++) {

		desc_new = irq_to_desc_alloc_node(new, node);

		if (!desc_new) {
@@ -3221,7 +3221,7 @@ unsigned int create_irq_nr(unsigned int irq_want, int node) 
			irq = new;

		break;

	}

	spin_unlock_irqrestore(&vector_lock, flags);

	raw_spin_unlock_irqrestore(&vector_lock, flags);



	if (irq > 0) {

		dynamic_irq_init(irq);
@@ -3261,9 +3261,9 @@ void destroy_irq(unsigned int irq) 
	desc->chip_data = cfg;



	free_irte(irq);

	spin_lock_irqsave(&vector_lock, flags);

	raw_spin_lock_irqsave(&vector_lock, flags);

	__clear_irq_vector(irq, cfg);

	spin_unlock_irqrestore(&vector_lock, flags);

	raw_spin_unlock_irqrestore(&vector_lock, flags);

}



/*
@@ -3800,9 +3800,9 @@ int __init io_apic_get_redir_entries (int ioapic) 
	union IO_APIC_reg_01	reg_01;

	unsigned long flags;



	spin_lock_irqsave(&ioapic_lock, flags);

	raw_spin_lock_irqsave(&ioapic_lock, flags);

	reg_01.raw = io_apic_read(ioapic, 1);

	spin_unlock_irqrestore(&ioapic_lock, flags);

	raw_spin_unlock_irqrestore(&ioapic_lock, flags);



	return reg_01.bits.entries;

}
@@ -3964,9 +3964,9 @@ int __init io_apic_get_unique_id(int ioapic, int apic_id) 
	if (physids_empty(apic_id_map))

		apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);



	spin_lock_irqsave(&ioapic_lock, flags);

	raw_spin_lock_irqsave(&ioapic_lock, flags);

	reg_00.raw = io_apic_read(ioapic, 0);

	spin_unlock_irqrestore(&ioapic_lock, flags);

	raw_spin_unlock_irqrestore(&ioapic_lock, flags);



	if (apic_id >= get_physical_broadcast()) {

		printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
@@ -4000,10 +4000,10 @@ int __init io_apic_get_unique_id(int ioapic, int apic_id) 
	if (reg_00.bits.ID != apic_id) {

		reg_00.bits.ID = apic_id;



		spin_lock_irqsave(&ioapic_lock, flags);

		raw_spin_lock_irqsave(&ioapic_lock, flags);

		io_apic_write(ioapic, 0, reg_00.raw);

		reg_00.raw = io_apic_read(ioapic, 0);

		spin_unlock_irqrestore(&ioapic_lock, flags);

		raw_spin_unlock_irqrestore(&ioapic_lock, flags);



		/* Sanity check */

		if (reg_00.bits.ID != apic_id) {
@@ -4024,9 +4024,9 @@ int __init io_apic_get_version(int ioapic) 
	union IO_APIC_reg_01	reg_01;

	unsigned long flags;



	spin_lock_irqsave(&ioapic_lock, flags);

	raw_spin_lock_irqsave(&ioapic_lock, flags);

	reg_01.raw = io_apic_read(ioapic, 1);

	spin_unlock_irqrestore(&ioapic_lock, flags);

	raw_spin_unlock_irqrestore(&ioapic_lock, flags);



	return reg_01.bits.version;

}