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Commit da7fedd9 authored by Trilok Soni's avatar Trilok Soni
Browse files

edac: Add support for Cortex A53 and A57 cache error detection 



This driver is snapshot from msm-3.10 upto this
commit (142c36711 - edac: cortex_arm64_edac: Use dbe irq only)
for this driver and adds the support for the ECC based error
detection driver for L1 and L2 cache.

Change-Id: I7b431ffb971cec612cd6ad846235260ea617c7ef
Signed-off-by: default avatarTrilok Soni <tsoni@codeaurora.org>
parent 49a08621

Documentation/devicetree/bindings/cache/arm64_cache_erp.txt

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* ARM Cortex A53 / A57 cache error reporting driver



Required properties:

- compatible: Should be "arm,arm64-cpu-erp"

- interrupts: List of hardware interrupts that may indicate an error condition

  in the CPU subsystem, or in the L1 / L2 caches. At least one interrupt entry

  is required.

- interrupt-names: Must contain one or more of the following IRQ types:

	"pri-dbe-irq" - double-bit error interrupt for primary cluster

	"sec-dbe-irq" - double-bit error interrupt for secondary cluster

	"pri-ext-irq" - external bus error interrupt for primary cluster

	"sec-ext-irq" - external bus error interrupt for secondary cluster

	"cci-irq"     - CCI error interrupt. If this property is present, having

			the 'cci' reg-base defined using the 'reg' property is

			recommended.

	"sbe-irq"     - Single-bit Error interrupt. Single-bit errors interrupts

			are generated by the pmu overflow interrupt, so this essentially

			is just the arm64 pmu interrupt. This is a percpu interrupt.

	At least one irq entry is required.



Optional properties:

- reg: Should contain physical address of the CCI register space

- reg-names: Should contain 'cci'. Must be present if 'reg' property is present

- qcom,apply-cti-pmu-wa: Indicates if the driver needs to apply the CTI PMU Workaround. Relevant for 8994V1.

- poll-delay-msec: Indicates how often the edac check callback should be called. Time in msec.



Example:

	cpu_cache_erp {

		compatible = "arm,arm64-cpu-erp";

		interrupt-names = "pri-dbe-irq",

				  "sec-dbe-irq",

				  "pri-ext-irq",

				  "sec-ext-irq";

		interrupts = <0 92 0>,

			     <0 91 0>,

			     <0 96 0>,

			     <0 95 0>;

	};

drivers/edac/Kconfig

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@@ -385,4 +385,44 @@ config EDAC_ALTERA_MC 
	  preloader must initialize the SDRAM before loading

	  the kernel.



config EDAC_CORTEX_ARM64

	depends on EDAC_MM_EDAC && ARM64

	bool "ARM Cortex A53/A57 L1/L2 Caches"

	help

	   Support for error detection and correction on the

	   ARM Cortex A53 and A57 CPUs. For debugging issues having to do with

	   stability and overall system health, you should probably say 'Y'

	   here.



config EDAC_CORTEX_ARM64_PANIC_ON_CE

	depends on EDAC_CORTEX_ARM64

	bool "Panic on correctable errors"

	help

	   Forcibly cause a kernel panic if an correctable error (CE) is

	   detected, even though the error is (by definition) correctable and

	   would otherwise result in no adverse system effects. This can reduce

	   debugging times on hardware which may be operating at voltages or

	   frequencies outside normal specification.



	   For production builds, you should definitely say 'N' here.



config EDAC_CORTEX_ARM64_DBE_IRQ_ONLY

	depends on EDAC_CORTEX_ARM64

	bool "Only check for parity errors when an irq is generated"

	help

	   In ARM64, parity errors will cause an interrupt

	   to be triggered but may also cause a data abort to

	   occur. Only check for EDAC errors for the interrupt.

	   If unsure, say no.



config EDAC_CORTEX_ARM64_PANIC_ON_UE

	depends on EDAC_CORTEX_ARM64

	bool "Panic on uncorrectable errors"

	help

	   Forcibly cause a kernel panic if an uncorrectable error (UE) is

	   detected. This can reduce debugging times on hardware which may be

	   operating at voltages or frequencies outside normal specification.



	   For production builds, you should probably say 'N' here.



endif # EDAC

drivers/edac/Makefile

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@@ -67,3 +67,4 @@ obj-$(CONFIG_EDAC_OCTEON_LMC) += octeon_edac-lmc.o 
obj-$(CONFIG_EDAC_OCTEON_PCI)		+= octeon_edac-pci.o



obj-$(CONFIG_EDAC_ALTERA_MC)		+= altera_edac.o

obj-$(CONFIG_EDAC_CORTEX_ARM64)		+= cortex_arm64_edac.o

drivers/edac/cortex_arm64_edac.c

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File added.

Preview size limit exceeded, changes collapsed.

include/soc/qcom/cti-pmu-irq.h

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/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef __MSM_CTI_PMU_IRQ_H

#define __MSM_CTI_PMU_IRQ_H



#include <linux/workqueue.h>



#ifdef CONFIG_MSM8994_V1_PMUIRQ_WA

void msm_enable_cti_pmu_workaround(struct work_struct *work);

struct coresight_cti *msm_get_cpu_cti(int cpu);

void msm_cti_pmu_irq_ack(int cpu);

#else

static inline void msm_enable_cti_pmu_workaround(struct work_struct *work) { }

static inline struct coresight_cti *msm_get_cpu_cti(int cpu) { return NULL; }

static inline void msm_cti_pmu_irq_ack(int cpu) { }

#endif

#endif