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Commit da46f936 authored by Rodrigo Vivi's avatar Rodrigo Vivi Committed by Daniel Vetter
Browse files

drm/i915: Introduce FBC False Color for debug purposes. 



With this bit enabled, HW changes the color when compressing frames for
debug purposes.

ALthough the simple way to enable a single bit is over intel_reg_write,
this value is overwriten on next update_fbc so depending on the workload
it is not possible to set this bit with intel-gpu-tools. So this patch
introduces a persistent way to enable false color over debugfs.

v2: Use DEFINE_SIMPLE_ATTRIBUTE as Daniel suggested
v3: (Ville) only do false color for IVB+ since according to spec bit is
    MBZ before IVB.
v4: We don't have FBC on valleyview nor on cherryview (Ben)
v5: s/!HAS_PCH_SPLIT/!HAS_FBC (Ville)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarBen Widawsky <ben@bwidawsk.net>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 7f3de833

drivers/gpu/drm/i915/i915_debugfs.c

+42 −0
Original line number Diff line number Diff line
@@ -1433,6 +1433,47 @@ static int i915_fbc_status(struct seq_file *m, void *unused) 
	return 0;

}



static int i915_fbc_fc_get(void *data, u64 *val)

{

	struct drm_device *dev = data;

	struct drm_i915_private *dev_priv = dev->dev_private;



	if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))

		return -ENODEV;



	drm_modeset_lock_all(dev);

	*val = dev_priv->fbc.false_color;

	drm_modeset_unlock_all(dev);



	return 0;

}



static int i915_fbc_fc_set(void *data, u64 val)

{

	struct drm_device *dev = data;

	struct drm_i915_private *dev_priv = dev->dev_private;

	u32 reg;



	if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))

		return -ENODEV;



	drm_modeset_lock_all(dev);



	reg = I915_READ(ILK_DPFC_CONTROL);

	dev_priv->fbc.false_color = val;



	I915_WRITE(ILK_DPFC_CONTROL, val ?

		   (reg | FBC_CTL_FALSE_COLOR) :

		   (reg & ~FBC_CTL_FALSE_COLOR));



	drm_modeset_unlock_all(dev);

	return 0;

}



DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,

			i915_fbc_fc_get, i915_fbc_fc_set,

			"%llu\n");



static int i915_ips_status(struct seq_file *m, void *unused)

{

	struct drm_info_node *node = m->private;
@@ -3957,6 +3998,7 @@ static const struct i915_debugfs_files { 
	{"i915_pri_wm_latency", &i915_pri_wm_latency_fops},

	{"i915_spr_wm_latency", &i915_spr_wm_latency_fops},

	{"i915_cur_wm_latency", &i915_cur_wm_latency_fops},

	{"i915_fbc_false_color", &i915_fbc_fc_fops},

};



void intel_display_crc_init(struct drm_device *dev)

drivers/gpu/drm/i915/i915_drv.h

+2 −0
Original line number Diff line number Diff line
@@ -637,6 +637,8 @@ struct i915_fbc { 
	struct drm_mm_node compressed_fb;

	struct drm_mm_node *compressed_llb;



	bool false_color;



	struct intel_fbc_work {

		struct delayed_work work;

		struct drm_crtc *crtc;

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -1540,6 +1540,7 @@ enum punit_power_well { 
/* Framebuffer compression for Ironlake */

#define ILK_DPFC_CB_BASE	0x43200

#define ILK_DPFC_CONTROL	0x43208

#define   FBC_CTL_FALSE_COLOR	(1<<10)

/* The bit 28-8 is reserved */

#define   DPFC_RESERVED		(0x1FFFFF00)

#define ILK_DPFC_RECOMP_CTL	0x4320c

drivers/gpu/drm/i915/intel_pm.c

+3 −0
Original line number Diff line number Diff line
@@ -309,6 +309,9 @@ static void gen7_enable_fbc(struct drm_crtc *crtc) 


	dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;



	if (dev_priv->fbc.false_color)

		dpfc_ctl |= FBC_CTL_FALSE_COLOR;



	I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);



	if (IS_IVYBRIDGE(dev)) {